Senior Lead Engineer - FCT

Quest Global; Bengaluru; On-site; INR 2,800,000 - 3,800,000; Full time

Job summary

Quest Global in Bengaluru seeks an experienced IC timing closure engineer to own the full chip timing closure process. You will ensure performance targets are met, perform STA and timing closure, and debug violations while defining critical constraints.

Preferred candidates have hands-on experience with Innovus/Fusion Compiler and formal tools, along with TCL/Python scripting and exposure to advanced nodes (7nm and below). BE/BTech/MTech in Electronics is required.

Qualifications

• Role requires ownership of full chip timing closure and meeting performance targets.
• Hands-on experience with STA and timing closure, debugging violations, and constraint definition.
• Exposure to FCT flow and ECO generation/interface timing closure.

Responsibilities

• Own full chip timing closure and ensure performance targets are met.
• Perform STA and timing closure
• Debug violations
• Define constraints
• FCT Flow Knowledge
• FCT ECO generation/Interface timing closure

Skills

PrimeTime/Tempus

StarRC

Formality LEC

TCL scripting

Python scripting

Advanced nodes (7nm+)

Education

BE/BTech/MTech in Electronics or related field

Tools

Innovus

Fusion Compiler

Job description

Job Requirements

At Quest Global, it’s not just what we do but how and why we do it that makes us different. With over 25 years as an engineering services provider, we believe in the power of doing things differently to make the impossible possible. Our people are driven by the desire to make the world a better place—to make a positive difference that contributes to a brighter future. We bring together technologies and industries, alongside the contributions of diverse individuals who are empowered by an intentional workplace culture, to solve problems better and faster.

Job Requirements

At Quest Global, it’s not just what we do but how and why we do it that makes us different. With over 25 years as an engineering services provider, we believe in the power of doing things differently to make the impossible possible. Our people are driven by the desire to make the world a better place—to make a positive difference that contributes to a brighter future. We bring together technologies and industries, alongside the contributions of diverse individuals who are empowered by an intentional workplace culture, to solve problems better and faster.

Role Overview

Own full chip timing closure and ensure performance targets are met.

Key Responsibilities

• Perform STA and timing closure
• Debug violations
• Define constraints
• FCT Flow Knowledge
• FCT ECO generation/Interface timing closure
  
  

Required Skills & Expertise

• PrimeTime / Tempus
• StarRC knowledge
• Formality LEC
• Exposure to Innovus / Fusion Compiler
  
  

Preferred Skills

• Strong TCL scripting capability
• Python scripting is a plus
• Experience in advanced nodes (7nm and below)
  
  

Experience

6–9 years

Education

BE/BTech/MTech in Electronics or related field

We are known for our extraordinary people who make the impossible possible every day. Questians are driven by hunger, humility, and aspiration. We believe that our company culture is the key to our ability to make a true difference in every industry we reach. Our teams regularly invest time and dedicated effort into internal culture work, ensuring that all voices are heard.

We wholeheartedly believe in the diversity of thought that comes with fostering a culture rooted in respect, where everyone belongs, is valued, and feels inspired to share their ideas. We know embracing our unique differences makes us better, and that solving the worlds hardest engineering problems requires diverse ideas, perspectives, and backgrounds. We shine the brightest when we tap into the many dimensions that thrive across over 21,000 difference-makers in our workplace.