Senior Engineer II - Backend Implementation

Microchip Technology; India; On-site; INR 2,800,000 - 3,800,000; Full time

Job summary

Microchip Technology Inc. in Bangalore, India, seeks an experienced Backend Implementation Engineer to perform STA for large SOCs. You will manage timing constraints generation, timing closure and Low Power checks, with strong experience in Tempus/Primetime.

The role requires ownership of full chip/sub-system implementation and a leadership mindset. Ideal candidates have 7+ years of STA experience, deep knowledge of Synthesis & STA tools, Verilog, and scripting skills in Perl/TCL/Python.

Qualifications

• B.E./B.Tech or M.Tech in Electronics required.
• 7+ years of STA experience in fast-paced environments.
• Strong knowledge of STA, timing closure and DFT insertion.

Responsibilities

• Perform STA timing closure for multi-million hierarchical designs.
• Lead and drive implementation activities within the team.
• Complete timing closure for blocks and top level in advanced nodes.
• Develop constraints/SDC and perform pre/post-layout timing closure.
• Perform CLP and LEC for full chip and block level.
• Possess experience with UPF/CPF as added advantage.
• Occasional travel as required.

Skills

STA

Timing closure

Scripting (Python/TCL/Perl)

Verilog knowledge

Team leadership

Communication skills

Education

B.E./B.Tech in Electronics

M.Tech in Electronics

Tools

Genus

Fusion Compiler

Primetime

Tempus

Conformal LEC

Job description

Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.

People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip's nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values ; we affectionately refer to it as the Aggregate System and it's won us countless awards for diversity and workplace excellence.

Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.

Visit our careers page to see what exciting opportunities and company perks await!

Company Description

Microchip Technology Inc. is a leading provider of embedded control applications. Our product portfolio comprises general purpose and specialized 8-bit, 16-bit, and 32-bit microcontrollers, 32-bit microprocessors, field-programmable gate array (FPGA) products, a broad spectrum of high-performance linear, mixed-signal, power management, thermal management, radio frequency (RF), timing, safety, security, wired connectivity and wireless connectivity devices, as well as serial Electrically Erasable Programmable Read Only Memory (EEPROM), Serial Flash memories, Parallel Flash memories, and serial Static Random Access Memory (SRAM). We also license Flash-IP solutions that are incorporated in a broad range of products.

Job Description

Microchip AES Design team looking for an experienced and motivated Backend Implementation Engineer to perform STA for larger SOCs. As a member of Implementation team, you will be responsible for timing constraints (SDC) generation, timing closure and Low Power checks for multiple blocks and top level. The candidate should have strong experience with STA tools like Tempus/Primetime. The candidate should have in depth knowledge of timing constraints.

Location: Bangalore, India

Requirements/Qualifications

Job Responsibilities

• The employee is responsible for implementation activities of multiple large & complex blocks & sub-system implementation from 16nm to 3nm and below technology nodes.
• The employee is expected to take ownership of Full Chip/Subsystem complex design & flow challenges, which would include:
• Perform STA timing closure for multi-million hierarchical complex designs.
• Lead and drive team members to complete Implementation activities.
• Complete timing closure for blocks & top level in advanced nodes.
• Develop constraints/SDC and perform pre & post-layout timing closure.
• Perform CLP and LEC for both full chip and block level.
• Experience on UPF/CPF would be an added advantage.
• Optimize design performance through timing closure and power optimization.
• Develop and maintain design constraints and timing models.
• Analyze and debug timing issues.
• Inserting DFT logic for both block and top level.
• Analyze Physical timing challenges and provide guidance for placement & CTS.
• Occasional travel needed.
• Use metric-driven techniques to help ensure first-pass working silicon.
• Communicate regularly with the implementation and project team to resolve issues, and communicate status to Project Management.

Job Qualifications

• This position requires at least B.E/B.Tech/M.Tech in Electronics with 7+ years of STA experience in a fast-paced environment with following experience.
• Expertise in Implementation activities: STA.
• Static Timing/Crosstalk Analysis and timing closure
• Must have understanding of DFT insertion.
• Expertise with Synthesis & STA Tools (Genus, Fusion Compiler, Primetime or Tempus).
• Experience on Conformal LEC and CLP will be added advantage.
• Strong programming knowledge in Perl, TCL, and/or Shell and Python Scripting
• Excellent oral and written communications skills to work with teams across the globe
• Strong understanding of timing closure and power optimization techniques
• Must have good understanding of Verilog.

Travel Time

0% - 25%