Senior IC Layout Engineer

Amber Solutions, Inc.; Bengaluru; Remote; INR 4,500,000 - 6,500,000; Full time

Benefits offered by this job

Competitive salary and benefits

Growth and development opportunities

Collaborative and innovative work环境

Impact on semiconductor industry

Job summary

AmberSemi is seeking a Senior IC Layout Engineer to join our semiconductor design team. You will develop full-custom layouts for analog, mixed-signal, and power management circuits in advanced BCD processes, focusing on high-current FETs and LDMOS devices.

You will collaborate with circuit designers, process engineers, and verification teams to deliver robust, production-ready layouts and support tapeout activities, while mentoring junior engineers and contributing to layout methodologies.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Microelectronics, or related field.
• 5+ years of custom IC layout experience in the semiconductor industry.
• Strong hands-on experience with BCD process technologies.
• Proven experience designing layouts for high-current power FETs and power management ICs.
• Deep understanding of electromigration, IR drop, ESD, latch-up, and thermal effects.

Responsibilities

• Develop full-custom IC layouts for analog, mixed-signal, and power management circuits in advanced BCD process technologies.
• Design and optimize layouts for high-current power FETs, LDMOS devices, current mirrors, gate drivers, regulators, charge pumps, and protection circuitry.
• Implement floorplanning, device matching, guard rings, shielding, isolation structures, and high-current routing strategies.
• Ensure layouts meet performance, reliability, density, and manufacturability requirements.
• Perform and resolve physical verification checks including DRC, LVS, ERC, EM/IR analysis, and antenna/density checks.
• Work closely with circuit designers to optimize parasitics, thermal distribution, current handling, and device matching.
• Support tapeout activities and contribute to layout methodology improvements and mentoring of junior layout engineers.

Skills

Custom IC layout

BCD process tech

Parasitics optimization

Team collaboration

Education

BSc/MSc in Electrical Engineering or Microelectronics

Tools

Calibre

Assura

PVS

Job description

We are seeking a highly motivated and detail-oriented Senior IC Layout Engineer to join our semiconductor design team developing advanced power management and mixed-signal integrated circuits using BCD technologies. The ideal candidate will have strong experience in custom IC layout for high-voltage and high-current power devices, including LDMOS and power FET structures, with a deep understanding of reliability, electromigration, ESD, latch-up, and manufacturability considerations.

This role involves close collaboration with circuit designers, process engineers, and verification teams to deliver robust and production-ready layouts for datacenter power applications.

Key Responsibilities

• Develop full-custom IC layouts for analog, mixed-signal, and power management circuits in advanced BCD process technologies.


• Design and optimize layouts for high-current power FETs, LDMOS devices, current mirrors, gate drivers, regulators, charge pumps, and protection circuitry.


• Implement floorplanning, device matching, guard rings, shielding, isolation structures, and high-current routing strategies.


• Ensure layouts meet performance, reliability, density, and manufacturability requirements.


• Perform and resolve physical verification checks including:


• DRC (Design Rule Check)


• LVS (Layout Versus Schematic)


• ERC (Electrical Rule Check)


• EM/IR analysis


• Antenna and density checks


• Work closely with circuit designers to optimize parasitics, thermal distribution, current handling, and device matching.


• Support tapeout activities


• Contribute to layout methodology improvements and mentoring of junior layout engineers.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Microelectronics, or related field.


• 5+ years of custom IC layout experience in semiconductor industry.


• Strong hands-on experience with BCD process technologies


• Proven experience designing layouts for high-current power FETs and power management ICs.


• Deep understanding of:


• Electromigration (EM)


• IR drop


• ESD protection


• Latch-up prevention


• Thermal effects in power devices


• Device matching and symmetry techniques


• Experience with common EDA layout tools such as:


• Calibre


• Assura/PVS


• Ability to interpret process documentation, reliability rules, and foundry requirements.


• Strong communication and teamwork skills.

What We Offer

• Competitive salary and benefits package.


• Opportunities for professional growth and development.


• A collaborative and innovative work environment.


• The chance to make a significant impact in the semiconductor industry.

Equal opportunities

AmberSemi is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.