Senior FPGA IP Design Engineer

Altera Corporation; Bengaluru; On-site; INR 2,000,000 - 4,000,000; Full time

Job summary

Altera Corporation in Bengaluru, India, seeks a Senior FPGA Soft IP Development Engineer to own architecture, micro-architecture, and RTL design of high-performance soft IP blocks, including AMBA AXI4 interconnects. You will collaborate with verification and physical design teams to ensure timing closure and portability across FPGA platforms.

The role requires 5+ years of RTL/FPGA experience, strong AXI4 expertise, and proficiency with Questa/Modelsim and VCS.

Qualifications

• We are seeking a Senior FPGA Soft IP Development Engineer with 5+ years of RTL/FPGA design experience.
• Deep hands-on knowledge of AMBA AXI4 protocol and high-speed memory interfaces.
• Proficiency with FPGA toolchains and EDA simulators; scripting in Python, Tcl or Perl.
• Bachelor’s or Master’s degree in Electrical Engineering or Computer Engineering.

Responsibilities

• Own architecture, micro-architecture, and RTL design of high-performance soft IP blocks.
• Define RTL for blocks such as schedulers, command pipelines, and system interfaces.
• Collaborate with verification to develop test plans and improve coverage.
• Assist physical design to resolve timing, power, and congestion issues.
• Provide RTL fixes and support to customers and field teams as needed.
• Apply CDC/RDC analysis within the design flow; mentor junior engineers.

Skills

RTL design

FPGA design

AMBA AXI4

Python

Tcl

Perl

Education

Bachelor’s or Master’s in Electrical or Computer Engineering

Tools

Siemens Questa/Modelsim

Synopsys VCS

Job description

## Senior FPGA IP Design EngineerApply: Bengaluru, Karnataka, India: Full time: Posted Today: R03235# **Job Details:**### ## **Job Description:**We are seeking a **Senior FPGA Soft IP Development Engineer** to own the architecture, micro-architecture, and parameterizable RTL design of high-performance soft intellectual property (IP) blocks. In this role, you will be responsible for developing critical system-level IP cores—including advanced AMBA AXI Interconnect IP - ensuring their portability, scalability, and timing closure across diverse FPGA architectures. **Responsibilities** * Own micro-architecture definition and RTL design for critical blocks such as schedulers, command pipelines, coherency/ordering logic, and system interfaces* Collaborate closely with the verification team to shape test plans and improve verification coverage* Work with the physical design team to understand and resolve timing, power, and congestion challenges* Work with the verification team on regression failure debug and root cause, and provide RTL fixes if necessary* Provide technical support to the FAE team on pre-sales customer engagements* Provide technical support to the AE team on post-sales customer deliveries* Apply working knowledge of CDC (Clock Domain Crossing) and RDC (Reset Domain Crossing) analysis within the design flow* Develop RTL micro-architecture from scratch* Provide technical guidance and mentorship to other engineers while remaining a hands-on individual contributor **Required Qualifications & Technical Skills*** **Education & Experience:** bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field with **5+ years** of dedicated RTL/FPGA design experience.* **Protocol Expertise:** Deep, hands-on knowledge of the **AMBA AXI4 protocol suite** and high-speed memory interfaces.* **Toolchains:** Proficiency with FPGA implementation tools and EDA simulation software (Siemens Questa/Modelsim, Synopsys VCS).* **Scripting:** Strong scripting skills in **Python, Tcl, or Perl** for build automation and test automation.### ## **Qualifications:**### ## **Job Type:**Regular### ## **Shift:**Shift 1 (India)### ## **Primary Location:**Bengaluru, Karnataka, India### ## **Additional Locations:**### ## **Posting Statement:**All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.