Senior Engineer -Low Power CLP

Arm; Bengaluru; Hybrid; INR 1,500,000 - 2,100,000; Full time

Job summary

Arm’s Solutions Engineering group is seeking an experienced verification engineer to strengthen signoff across low-power and LEC flows for complex SoC/IP programs. You will implement and debug CLP/VCLP, UPF/CPF, and LEC methodologies to ensure power intent correctness and robust signoff.

You will develop automated verification flows using TCL, Python and Perl, collaborate with design, verification and implementation teams, and participate in RTL-to-GDS signoff for quality silicon tapeout in a

Qualifications

• 5+ years of relevant experience in logical signoff and low-power structural verification.
• Strong experience with UPF/CPF and SystemVerilog.
• Hands-on experience with low-power verification tools such as CLP or VCLP.
• Experience with Logic Equivalence Checking (LEC) and power-aware LEC, with ability to analyze and resolve verification failures.
• Ability to debug CLP/VCLP and LEC issues and drive them through closure.
• Understanding of synthesis and Place & Route (P&R) flows is an advantage.
• Ability to collaborate across design, verification, and implementation teams to support signoff.

Responsibilities

• Perform low-power verification using CLP or VCLP.
• Verify UPF implementation across RTL, netlist, and physical design stages.
• Analyze, debug, and resolve CLP structural, rule-based, and power-aware verification failures.
• Implement SoC-level low-power structural checks and debug issues through closure.
• Perform RTL-to-Synthesis, Synthesis-to-P&R, and ECO logic equivalence verification using Cadence Conformal LEC.
• Develop, automate, and maintain robust LEC flows and signoff methodologies.
• Drive LEC failure resolution and closure, and generate comprehensive signoff reports.
• Implement and debug SoC-level flat LEC runs through signoff.
• Develop TCL, Perl, and Python scripts to automate verification tasks.
• Build and maintain reusable verification flows and debug utilities to improve efficiency and scalability.
• Drive methodology enhancements for low-power verification signoff and efficient resolution of verification aborts.

Skills

Low-power verification

LEC/Formality

SystemVerilog

UPF/CPF

Signoff experience

CLP/VCLP

Scripting (TCL/Python/Perl)

Tools

Cadence Conformal Low Power

Synopsys VCLP

Cadence Conformal LEC

Job description

Job Description: In Arm's Solutions Engineering group, our primary focus extends beyond the development of advanced System-on-Chips (SoCs). In the endeavour to deliver a quality silicon we need to ensure all our signoff checks across various domains are diligently performed. Delivering quality silicon leads to quality rewards and every effort and skill is recognized and appreciated at ARM. Our responsibilities also encompass improvising methodologies, influencing EDA tools and build a knowledge base which will help in our product design. Learning and sharing knowledge is part of ARM culture and is very much appreciated and encouraged. If you're interested in working with a team of collaborative and smart engineers responsible for validating RTL-to-Gate and Gate-to-GDS implementations, ensuring power intent correctness, and enabling high-quality silicon tapeout.

Responsibilities

Low Power structural check

• Perform low-power verification using Cadence Conformal Low Power (CLP) or Synopsys VCLP.
• Verify and validate UPF implementation across RTL, netlist, and physical design stages.
• Perform power-aware equivalence checking and resolve identified issues.
• Analyze, debug, and resolve CLP structural, rule-based, and power-aware verification failures.
• Implement SoC-level low-power structural checks and debug issues through closure.

Logical Equivalence Checking (LEC/Formality)

• Perform RTL-to-Synthesis, Synthesis-to-P&R, and ECO logic equivalence verification using Cadence Conformal LEC.
• Analyze, debug, and resolve non-equivalences and aborts across different stages of the design flow.
• Develop, automate, and maintain robust LEC flows and signoff methodologies.
• Drive LEC failure resolution and closure, and generate comprehensive signoff reports.
• Implement and debug SoC-level flat LEC runs through signoff.

Methodology And Automation

• Develop TCL, Perl, and Python scripts to automate verification tasks and improve productivity.
• Build and maintain reusable verification flows and debug utilities to improve efficiency and scalability.
• Drive methodology enhancements for low-power verification signoff and efficient resolution of verification aborts.

Required Skills And Experience

• We are looking for a candidate with 5+ years of relevant experience in logical signoff and low-power structural verification for sophisticated SoC and IP development programs.
• Strong experience with low-power design and verification, including hands‑on knowledge of UPF/CPF and SystemVerilog.
• Hands‑on experience with low-power verification tools such as Cadence Conformal Low Power (CLP) or Synopsys VCLP.
• Experience with Logic Equivalence Checking (LEC) and power‑aware LEC, with strong skills in analyzing and resolving verification failures.
• Ability to effectively debug CLP/VCLP and LEC issues and drive them through closure.
• Understanding of synthesis and Place & Route (P&R) flows is an advantage.
• Ability to collaborate across design, verification, and implementation teams to support successful signoff of complex SoC and IP designs.

Our 10x Mindset

At Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset

Use of AI in Your Application

At Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact [e-mail] so we can support you.

Recruitment Adjustments and Accommodations

At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email [e-mail] . To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.

Hybrid Working

Arm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.

Equal Opportunities

Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.