Senior Engineer II - IP Verification

FHLB Des Moines; Hyderabad; On-site; INR 2,500,000 - 4,000,000; Full time

Job summary

FHLB Des Moines requires a senior verification engineer to own verification of high‑speed interfaces and AMBA protocols. You will architect test benches, code test cases, and improve coverage, while collaborating with design teams to ensure robust IP sign‑offs. Strong English communication is essential.

The role demands 7+ years of digital IP/SoC verification experience, experience with Siemens tools, and the ability to deliver large projects across blocks and system levels in a team environment.

Qualifications

• BSEE/MSEE in Electrical/ Electronics or Electronics and Telecommunication.
• 7+ years of digital IP/SoC verification experience.
• Proven block and system level verification track record.
• Excellent written and verbal English communication.
• Experience building verification environments with SV/UVM.
• Familiarity with AMBA, DSP, DDR IP cores and FPGA design flows.
• Proficiency in scripting (Tcl, Perl) for verification tasks.

Responsibilities

• Architect and implement test benches optimized for features under test.
• Develop and debug test cases; improve verification coverage.
• Review verification designs to ensure robust IP sign-off.
• Analyze coverage metrics and define additional test cases.
• Collaborate with design and other teams; communicate clearly.

Skills

AMBA protocols

SV/UVM test benches

Verification environments

Debug & analysis

C language

MATLAB

Python/Perl/Tcl scripting

System-level design

DSP/DDR IP cores

FPGA verification (Microchip/Formerly)

Education

BSEE/MSEE (Electrical/Electronics/ETC)

Tools

Siemens verification tools

Job description

Job Description

• Verification ownership of one or more features in the high-speed serial interfaces/ protocols, experience on AMBA protocols, DSP, DDR IP cores
• Developing a robust test bench, optimized for the specific feature/DUT
• Explore innovative verification methodologies to continuously push the quality and efficiency of test benches and process improvements
• Individual contributor in the Verification Tasks - Architect test benches, coding of test cases, debug, verification coverage improvement, etc.
• Will contribute to technical review of verification designs, etc. and ensure a robust and bug free IP sign-off and improve to achieve high-quality deliveries
• The candidate should be able to analyze the coverage metrics and improve them with definition of additional test cases
• The candidate will work in a project and team-oriented environment and must be able to collaborate with other teams
• The role also requires close collaboration with design team. Hence, we are looking for candidates with strong communication skill - both written and verbal.

Requirements/Qualifications

• BSEE/ MSEE under Electrical or Electronics or Electronics and Telecommunications Engineering department
• 7+ years relevant digital IP/SoC development experience
• A demonstrable track record of verification both at the block and system level
• Excellent written and verbal communication skills in English
• History of working to defined processes and procedures
• Ability to deliver complex and large projects that span outside of immediate job area
• Strong debugging and analytical skills and independent problem-solving ability
• Proficiency in building verification environments, writing test benches, testcases and coverage points, etc. using SV/UVM based test benches
• Expert user of Siemens verification tools and verification IPs
• Working experience on scripting tools used for verification (tcl, perl, etc).
• System level design experience
• Experience designing solutions with Microchip (formerly Microsemi) FPGAs
• Knowledge of processor based systems
• MATLAB and C language programming skills
• Exercises judgement in selecting methods, techniques and evaluation criteria for obtaining result

Travel Time

0% - 25%