Senior Engineer - IC Verification

Silabs India; Hyderabad; On-site; INR 2,400,000 - 4,200,000; Full time

Benefits offered by this job

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Job summary

Silicon Labs in Hyderabad seeks a Design Verification Engineer to work with IC Design, System, and Architecture teams on verification planning and execution for next-gen Wireless MCU SoCs.

You will develop testbenches, use constrained-random stimulus, and apply formal methods to ensure design quality, power behavior, and use-case validation across block/IP and SoC levels.

Qualifications

• Candidates should have strong fundamentals in IC design verification.
• Experience with testbenches and verification components using SystemVerilog and UVM is required.
• Strong analytical and debugging skills along with collaboration in cross-functional teams.

Responsibilities

• Perform block-and-IP level verification to validate functionality and compliance.
• Develop and execute verification plans based on architecture and design specifications.
• Architect, implement, and maintain testbenches using SystemVerilog and UVM with constrained-random stimulus, checkers, and assertions.
• Define and analyze functional coverage; drive closure through coverage and regression analysis.
• Apply formal verification techniques to mixed-signal IP integration including RNM approaches.
• Verify and debug low-power design behavior and power-management interactions.
• Collaborate with IC Design, System, and Architecture teams to validate use-cases and SoC benches.

Skills

Python

Debugging

Communication

Scripting

Education

BE/BTech or ME/MTech in Electrical/Electronics/VLSI

Tools

SystemVerilog

UVM

UPF

SVA

AMBA AXI/APB

C

Job description

Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world's most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets. Learn more at www.silabs.com .

Meet the Team

The IoT Digital team is a state-of-the-art IC design team focused on producing world-class Wireless MCU SoCs. The team is responsible for architecture specification, design, verification, and implementation of these SoCs, which combine an embedded CPU system with analog and digital peripherals, advanced security, state-of-the-art power management, and best-in-class radios for a wide range of wireless IoT applications and standards.

About the Role

As a Design Verification Engineer, you will work closely with IC Design, System, and Architecture teams to develop and execute verification plans for the next generation of IoT chips. You will contribute across block and IP verification, mixed-signal integration, and SoC-level use-case validation. The role is suited to an Engineer or Senior Engineer at IC3; candidates with strong fundamentals will be considered alongside experienced candidates. You will help ensure that designs meet their specifications through well-planned stimulus, assertions, coverage, and debug. You will also contribute to low-power verification and improve the flows and methodologies used to develop and integrate IP. This is an opportunity to contribute directly to the quality and delivery of next-generation Wireless MCU SoCs.

Responsibilities

• Perform block-and-IP-level verification to validate functionality, performance, and compliance with design requirements.
• Develop and execute verification plans based on architecture and design specifications, defining appropriate scenarios and closure criteria.
• Architect, implement, and maintain testbenches using SystemVerilog and UVM, including constrained-random stimulus, checkers, and assertions.
• Define and analyze functional coverage, identify gaps, and drive verification closure through coverage and regression analysis.
• Apply formal verification techniques to mixed-signal IP integration, including verification using real-number models (RNM).
• Integrate and verify SoC benches; define, test, and debug system use cases in collaboration with IC Design, System, and Architecture teams.
• Verify and debug low-power design behavior, including relevant power-management scenarios and interactions.
• Investigate failures, perform root-cause analysis, and communicate issues and verification status clearly to cross-functional teams.
• Improve verification flows and methodologies to streamline IP development, reuse, and integration.
• Contribute to reviews of specifications, verification plans, testbenches, and results, incorporating feedback to improve quality.
• Share reusable practices and technical learnings with the verification team.

Requirements

• B.E./B.Tech or M.E./M.Tech in Electrical Engineering, Electronics, Computer Engineering, VLSI, or a related field.
• For Senior Engineer positions, typically 5 or more years of relevant IC design or Design Verification experience; Engineer-level candidates with a strong foundation will also be considered.
• Industry experience developing testbenches and verification components using SystemVerilog and UVM.
• Knowledge of verification planning, constrained-random testing, SystemVerilog Assertions (SVA), and functional coverage analysis.
• Experience with scripting or programming languages such as Python, Perl, Shell, or Tcl.
• Working knowledge of software or firmware coding in C and the ability to work with design specifications and debug simulation results.
• Understanding of low-power implementation and verification concepts, including UPF.
• Strong analytical, debugging, communication, and collaboration skills.

Preferred Qualifications

• Experience with wireless SoCs, low-power IoT silicon, or MCU subsystems.
• Experience with AMBA interconnect protocols, including AXI and APB, and embedded systems.
• Exposure to mixed-signal verification, real-number modeling (RNM), or SPICE-based simulation.
• Experience with formal verification, SoC bench integration, or low-power verification using UPF.
• Experience verifying security-related IP or features is an advantage.

"Experience with artificial intelligence (AI) powered tools and technologies used to enhance productivity, analysis, and decision-making"

Benefits & Perks:

Not only will you be joining a highly skilled and tight-knit team where every engineer makes a significant impact on the product; we also strive for good work/life balance and to make our environment welcoming and fun.

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