Senior Engineer - Emulation

Larsen & Toubro; Bengaluru; On-site; INR 1,200,000 - 2,100,000; Full time

Job summary

Larsen & Toubro seeks an experienced FPGA Prototyping & Emulation engineer in Bengaluru to own multi‑FPGA prototyping, synthesis/P&R, timing closure and bitfile generation. You will bring up boards, support emulator models on ZeBu/Veloce, and collaborate with Design, DV, Firmware and Board teams to resolve complex issues.

You will drive automation, performance optimization and debug methodologies, mentoring junior engineers while delivering on project milestones and quality

Qualifications

• Experience in FPGA prototyping and emulation workflows for complex SoC/ASIC designs.
• Hands-on with RTL prep, synthesis, P&R, and bitfile generation.
• Ability to analyze and resolve timing, QoR, and resource issues in multi‑FPGA systems.

Responsibilities

• Execute end-to-end FPGA prototyping and emulation for SoC/ASIC designs, including RTL prep, synthesis, P&R, and bitfile generation.
• Own FPGA prototype bring-up on platforms like HAPS and Protium; manage P&R and timing closure.
• Support multi‑FPGA partitioning, inter‑FPGA connectivity, timing analysis, and board bring‑up including JTAG and interfaces like SPI/I2C/UART/PCIe.
• Develop automation in TCL/Perl/Python for builds, regression, and log analysis to improve QoR and timing.
• Collaborate with Design, DV, Firmware, Software and Board teams to debug and resolve issues; mentor junior engineers.

Skills

FPGA prototyping

Emulation

RTL analysis

Synthesis/P&R

Timing analysis

Board bring‑up

JTAG/Debug

Python

Perl

TCL scripting

Tools

HAPS

Protium

ZeBu

Veloce

SPI/I2C/UART/PCIe interfaces

PCB/board bring‑up tools

Job description

Role Summary

Execute and own FPGA prototyping and emulation activities for complex SoC designs, with primary focus on multi-FPGA prototyping, synthesis/P&R, timing closure, bitfile generation, board bring-up and system-level debug. Support emulator model bring-up on ZeBu/Veloce and collaborate with Design, DV, Firmware and Board teams to resolve issues. Drive assigned technical workstreams, automation and productivity improvements while providing hands‑on technical guidance to junior engineers.

• Execute end-to-end FPGA prototyping and emulation activities for SoC/ASIC designs, covering RTL preparation, synthesis, partitioning, P&R, bitfile generation, board bring-up and validation.
• Take ownership of FPGA prototype model bring‑up on platforms such as HAPS, Protium and other FPGA-based prototyping systems.
• Support multi‑FPGA partitioning and implementation, including partition optimization, FPGA resource utilization, inter‑FPGA connectivity, pin utilization and routing challenges.
• Perform FPGA synthesis, P&R and timing analysis, identify implementation bottlenecks and work on resolving timing violations, congestion and resource issues.
• Support clock and reset implementation for FPGA prototypes, including analysis of ASIC clock structures and development/application of appropriate FPGA constraints.
• Drive FPGA board bring‑up and debug, including JTAG, clocks, resets, memories and SoC interfaces such as SPI, I2C, UART, MDIO, PCIe and other relevant interfaces.
• Develop, generate and validate FPGA bitfiles and support deployment on prototype hardware.
• Perform emulator model bring‑up and validation on platforms such as ZeBu and Veloce, including compilation, model configuration, basic connectivity validation and debug.
• Support FPGA prototype and emulator debug using waveform/debug tools, FPGA probes, logs and hardware/software correlation.
• Analyze RTL and implementation reports to identify synthesis, P&R, timing and emulation‑related issues, and work with RTL/DV teams to resolve them.
• Work closely with Design, DV, SV, Firmware, Software and Board teams to reproduce, debug and close issues encountered during FPGA prototype and emulator bring‑up.
• Support prototype/emulator regression execution, analyse failures and ensure issues are properly documented and tracked to closure.
• Develop and maintain TCL/Perl/Python automation for FPGA builds, configuration, regression, log analysis, timing/QoR extraction and repetitive debug activities.
• Monitor and improve FPGA build time, implementation QoR, timing, resource utilisation and prototype execution performance.
• Support evaluation and adoption of new FPGA boards, prototyping platforms and emulator capabilities under the guidance of senior technical leadership.
• Contribute to defining and improving FPGA prototyping and emulation flows, checklists and debug methodologies based on project experience.
• Take ownership of assigned technical workstreams and ensure milestones, deliverables and quality objectives are achieved within the project schedule.
• Act as a technical point of contact for assigned FPGA/emulation areas, providing status, issues, dependencies and recovery plans to the technical lead.
• Mentor junior engineers on day‑to‑day FPGA prototyping, implementation, bring‑up and debug activities.

Role Summary

Execute and own FPGA prototyping and emulation activities for complex SoC designs, with primary focus on multi‑FPGA prototyping, synthesis/P&R, timing closure, bitfile generation, board bring‑up and system‑level debug. Support emulator model bring‑up on ZeBu/Veloce and collaborate with Design, DV, Firmware and Board teams to resolve issues. Drive assigned technical workstreams, automation and productivity improvements while providing hands‑on technical guidance to junior engineers.

Roles & Responsibilities

• Execute end-to-end FPGA prototyping and emulation activities for SoC/ASIC designs, covering RTL preparation, synthesis, partitioning, P&R, bitfile generation, board bring‑up and validation.
• Take ownership of FPGA prototype model bring‑up on platforms such as HAPS, Protium and other FPGA‑based prototyping systems.
• Support multi‑FPGA partitioning and implementation, including partition optimisation, FPGA resource utilisation, inter‑FPGA connectivity, pin utilisation and routing challenges.
• Perform FPGA synthesis, P&R and timing analysis, identify implementation bottlenecks and work on resolving timing violations, congestion and resource issues.
• Support clock and reset implementation for FPGA prototypes, including analysis of ASIC clock structures and development/application of appropriate FPGA constraints.
• Drive FPGA board bring‑up and debug, including JTAG, clocks, resets, memories and SoC interfaces such as SPI, I2C, UART, MDIO, PCIe and other relevant interfaces.
• Develop, generate and validate FPGA bitfiles and support deployment on prototype hardware.
• Perform emulator model bring‑up and validation on platforms such as ZeBu and Veloce, including compilation, model configuration, basic connectivity validation and debug.
• Support FPGA prototype and emulator debug using waveform/debug tools, FPGA probes, logs and hardware/software correlation.
• Analyze RTL and implementation reports to identify synthesis, P&R, timing and emulation‑related issues, and work with RTL/DV teams to resolve them.
• Work closely with Design, DV, SV, Firmware, Software and Board teams to reproduce, debug and close issues encountered during FPGA prototype and emulator bring‑up.
• Support prototype/emulator regression execution, analyse failures and ensure issues are properly documented and tracked to closure.
• Develop and maintain TCL/Perl/Python automation for FPGA builds, configuration, regression, log analysis, timing/QoR extraction and repetitive debug activities.
• Monitor and improve FPGA build time, implementation QoR, timing, resource utilisation and prototype execution performance.
• Support evaluation and adoption of new FPGA boards, prototyping platforms and emulator capabilities under the guidance of senior technical leadership.
• Contribute to defining and improving FPGA prototyping and emulation flows, checklists and debug methodologies based on project experience.
• Take ownership of assigned technical workstreams and ensure milestones, deliverables and quality objectives are achieved within the project schedule.
• Act as a technical point of contact for assigned FPGA/emulation areas, providing status, issues, dependencies and recovery plans to the technical lead.
• Mentor junior engineers on day‑to‑day FPGA prototyping, implementation, bring‑up and debug activities.

Core Ownership Areas

FPGA Prototyping – Primary

HAPS | Protium | Multi‑FPGA Partitioning | Synthesis | P&R | Timing Closure | Clock/Reset | Bitfile Generation | FPGA Board Bring‑up | FPGA Debug | QoR Optimization

Emulation – Supporting/Hands‑on

ZeBu | Veloce | Emulator Model Bring‑up | Compilation | Connectivity Validation | Debug | Regression

Execution & Productivity

RTL Analysis | HW/SW Debug | Regression | Automation | Issue Tracking | Cross‑functional Debug | Technical Documentation