Senior Engineer Design Verification - Rx

GreenWave Radios™; Bengaluru; On-site; INR 1,800,000 - 2,800,000; Full time

Benefits offered by this job

Stock options

Learning opportunities

Leave benefits

Job summary

InnoPhase Inc., DBA GreenWave Radios Bangalore is looking for a Senior Engineer - Design Verification to join our fast-paced and motivated team to drive excellence in our 5G products. This role is an excellent opportunity for someone that enjoys driving the critical path and making a significant impact in launching products into the market and winning!

You will verify ORAN packet processing blocks, develop UVM testbenches, and collaborate with RTL, FW and architecture teams to ensure on-time

Qualifications

• 5+ years of experience in ORAN protocol design verification using reference models.
• Experience integrating Python/C++ models into UVM environments and building Agents, Scoreboards.
• Proficient in SystemVerilog, Verilog, UVM and scripting languages.
• Experience with Cadence tools and DV metrics extraction.
• Full lifecycle verification: test plan, testbench, coverage closure.

Responsibilities

• Verify ORAN packet processing blocks using internal Python Model.
• Verify high-speed SERDES interfaces such as PCIe, etc.
• Develop UVM testbench environment and execute verification cases to verify RTL design.
• Construct SoC level testbench re-using verification components at IP/Subsystem level.
• Develop and execute verification plans with architects and designers.
• Construct HW/SW Co-Verification environment - test-benches, APIs, sequences; debug use-cases.
• Active COCOTB based simulation.
• Use Claude to develop/close tasks.
• Involvement in analog simulations to validate RF interface.
• Gain exposure to modelling (TLM), HW emulation/acceleration, and SW-driven verification.
• Debug test cases and report verification results to achieve coverage goals.
• Work with FW team to convert DV sequence to FW drivers.
• Support emulation, FPGA, prototyping efforts.
• Maintain automated verification flows in Python, Perl/Shell.

Skills

ORAN protocol verification

Python/C++ modelling

UVM environment development

SystemVerilog/Verilog

DV testbench design

Constrained random verification

RTL verification

Scripting: Python, Tcl/Shell

Education

Master's and/or Bachelor's degree in Engineering (EC/EE/CS)

Tools

Cadence vManager

UVM

Verilog/SystemVerilog

Job description

InnoPhase Inc., DBA GreenWave Radios, is at the forefront of innovation in Open RAN digital radios. Our cutting-edge solutions, powered by the Hermes64 RF SoC, are designed to enhance network energy efficiency while dramatically reducing operational expenses, with purpose-built silicon that is the heart of ORAN-based active antenna arrays.

Headquartered in San Diego, California, GreenWave Radios has established itself as a pioneer in delivering power-efficient digital-to-RF solutions. The company is supported by a talented team of over 100 engineers spread across four global R&D facilities. With an extensive portfolio of more than 120 global patents, GreenWave Radios continues to push the boundaries of radio technology and innovation.

InnoPhase Inc., DBA GreenWave Radios and Synergic Emergence have a co-employment relationship. For over three years, GreenWave Radios has partnered with Synergic Emergence, a professional employment organization provider, to offer our employees the best benefits and services. This arrangement means that Synergic Emergence provides employee pay checks and benefits, and GreenWave Radios will provide employment, evaluation, and advancement. By outsourcing some HR functions, GreenWave Radios can focus on what we do best - developing and implementing highly innovative SOC cellular radio integrated circuit products.

Job Description

InnoPhase Inc., DBA GreenWave Radios Bangalore is looking for a Senior Engineer - Design Verification to join our fast-paced and motivated team to drive excellence in our 5G products. This role is an excellent opportunity for someone that enjoys driving the critical path and making a significant impact in launching products into the market and winning!

Key Responsibilities:

• You will be working within DV team on verifying ORAN packet processing blocks using internal developed reference Python Model.
• Work on high speed SERDES interface verification such as PCIE but not limited to.
• Develop UVM testbench environment and execute verification cases to verify RTL design in bit true and cycle accurate.
• Construct SoC level testbench re-using verification components developed at the IP/ Subsystem level. Test bench architecture for random/directed testing, stimulus generation, and integration of custom and off the shelf VIP/UVCs.
• Develop and execute verification plans based on design specifications and collaboration with architects and designers.
• Construct HW/SW Co-Verification environment - test-benches, use-cases, APIs, sequences. Execute and Debug use-cases.
• Actively working COCOTB based simulation
• Usage of Claude to Develop/close the existing task.
• Involvement in Analog based simulations to validate the RFA interface
• Be part of a dynamic and functionally diverse team with opportunities for gaining exposure to modelling (TLM), HW emulation/acceleration, and SW driven verification.
• Debug test cases and report verification result to achieve expected code/functional coverage metrics. Utilize constrained random verification, functional coverage, code coverage and assertions to achieve goals.
• Work with FW team to convert DV sequence to FW drivers
• Support emulation, FPGA, prototyping efforts.
• Implement and maintain automated verification flows in languages such as Python, Perl/ Shell scripts.

Job Requirements :

• Master's and/or bachelor's degree in engineering (or equivalent) in EC/ EE/ CS.
• 5 or more years of experience in ORAN protocol design verification using reference models.
• Hands-on experiences in integrating Python/C++ models to UVM environment and create Agents, Scoreboards components for network functional blocks.
• Experiences in Cadence vManager for DV metrics extraction and regression
• Good understanding of the complete verification life cycle (test plan, testbench through coverage closure).
• Expertise in developing testbench environment and verification components (Monitor, Scoreboard, Driver, Agent etc) from scratch.
• Proficient in SystemVerilog, Verilog, UVM and C; and scripting languages like Python, Perl and Tcl/Shell.
• Experience in developing IP/ Subsystem/ chip-level SystemVerilog and UVM based
• Experiences in GIT, JIRA, MS office suites

Benefits

• Competitive salary and stock options.
• Learning and development opportunities.
• Earned, Casual, Sick & parental leaves.