Senior Engineer Design Verification - Tx

GreenWave Radios™; Bengaluru; On-site; INR 900,000 - 1,500,000; Full time

Benefits offered by this job

Competitive salary

Stock options

Learning and development

Employer paid health insurance

Leaves (earned, casual, sick & parenal

Job summary

GreenWave Radios Bangalore is seeking a Senior Engineer - Design Verification to join our fast-paced DV team to drive excellence in 5G products. This role focuses on verification plans and developing UVM-based testbenches to validate DSP blocks and RTL designs.

The candidate will gain exposure to MATLAB/Python integration, HW/SW co-verification, and automated verification flows, with a strong emphasis on SystemVerilog and UVM. Emphasis on 5G product readiness and quality.

Qualifications

• Master's and/or bachelor's degree in engineering (EC/EE/CS).
• 5+ years of experience in DSP blocks design verification using reference models.
• Experience integrating MATLAB/Python models into UVM environment and creating Agents/Scoreboards.
• Knowledge of wireless communication theories (SNR, IQ constellations, FFT, OFDM, MIMO).
• Cadence vManager for DV metrics extraction and regression.
• Proficient in SystemVerilog, Verilog, UVM, and C; scripting with Python, Perl, Tcl/Shell.

Responsibilities

• Verify HW wireless DSP blocks using internal MATLAB/Python reference models.
• Develop UVM testbench environments and execute verification cases for RTL design.
• Construct SoC-level testbenches reusing IP/Subsystem verification components.
• Develop and execute verification plans based on design specs with architects/designers.
• Create HW/SW co-verification environments and debugging use-cases.
• Assist in emulation, FPGA, and prototyping efforts.
• Automate verification flows with Python, Perl/Shell.

Skills

SystemVerilog/UVM

DSP blocks

MATLAB/Python

Verilog

C

Python scripting

RTL verification

UVM environment

Education

Master's/Bachelor's in Engineering (EC/EE/CS)

Tools

Cadence vManager

GIT

JIRA

Job description

InnoPhase Inc., DBA GreenWave Radios™, is at the forefront of innovation in Open RAN digital radios. Our cutting-edge solutions, powered by the Hermes64 RF SoC, are designed to enhance network energy efficiency while dramatically reducing operational expenses, with purpose-built silicon that is the heart of ORAN-based active antenna arrays.

Headquartered in San Diego, California, GreenWave Radios™ has established itself as a pioneer in delivering power-efficient digital-to-RF solutions. The company is supported by a talented team of over 100 engineers spread across four global R&D facilities. With an extensive portfolio of more than 120 global patents, GreenWave Radios™ continues to push the boundaries of radio technology and innovation.

InnoPhase Inc., DBA GreenWave™ Radios and Synergic Emergence have a co-employment relationship. For over three years, GreenWave Radios has partnered with Synergic Emergence, a professional employment organization provider, to offer our employees the best benefits and services. This arrangement means that Synergic Emergence provides employee pay checks and benefits, and GreenWave Radios will provide employment, evaluation, and advancement. By outsourcing some HR functions, GreenWave Radios can focus on what we do best – developing and implementing highly innovative SOC cellular radio integrated circuit products.

Job Description

InnoPhase Inc., DBA GreenWave™ Radios Bangalore is looking for a Senior Engineer - Design Verification to join our fast-paced and motivated team to drive excellence in our 5G products. This role is an excellent opportunity for someone that enjoys driving the critical path and making a significant impact in launching products into the market and winning!

Key Responsibilities:

• You will be working within DV team on verifying HW wireless DSP blocks using internal developed reference MATLAB/Python Model.
• Develop UVM testbench environment and execute verification cases to verify RTL design in bit true and cycle accurate.
• Construct SoC level testbench re-using verification components developed at the IP/ Subsystem level. Test bench architecture for random/directed testing, stimulus generation, and integration of custom and off the shelf VIP/UVCs.
• Develop and execute verification plans based on design specifications and collaboration with architects and designers.
• Construct HW/SW Co-Verification environment - test-benches, use-cases, APIs, sequences. Execute and Debug use-cases.
• Be part of a dynamic and functionally diverse team with opportunities for gaining exposure to modelling (TLM), HW emulation/acceleration, and SW driven verification.
• Debug test cases and report verification result to achieve expected code/functional coverage metrics. Utilize constrained random verification, functional coverage, code coverage and assertions to achieve goals.
• Assist in emulation, FPGA, prototyping efforts.
• Implement and maintain automated verification flows in languages such as Python, Perl/ Shell scripts.

Job Requirements:

• Master's and/or bachelor's degree in engineering (or equivalent) in EC/ EE/ CS.
• 5 or more years of experience in DSP blocks(FFT, FIR, IIR, AGC, Interpolation/Decimation Filters, Up/Down Converter) design verification using reference models.
• Hands-on experiences in integrating MATLAB/Python models to UVM environment and create Agents, Scoreboards components for DSP blocks.
• Knowledge of wireless communication theories (SNR, IQ constellations, FFT, OFDM, MIMO)
• Experiences in Cadence vManager for DV metrics extraction and regression
• Good understanding of the complete verification life cycle (test plan, testbench through coverage closure).
• Expertise in developing testbench environment and verification components (Monitor, Scoreboard, Driver, Agent etc) from the scratch.
• Proficient in SystemVerilog, Verilog, UVM and C; and scripting languages like Python, Perl and Tcl/Shell.
• Experience in developing IP/ Subsystem/ chip-level SystemVerilog and UVM based
• Experiences in GIT, JIRA, MS office suites
• Competitive salary and stock options.
• Learning and development opportunities.
• Employer paid health Insurance.
• Earned, Casual, Sick & parental leaves.

Voluntary Self-Identification

For government reporting purposes, we ask candidates to respond to the below self-identification survey.Completion of the form is entirely voluntary. Whatever your decision, it will not be considered in the hiringprocess or thereafter. Any information that you do provide will be recorded and maintained in aconfidential file.

As set forth in GreenWave Radios™’s Equal Employment Opportunity policy,we do not discriminate on the basis of any protected group status under any applicable law.

If you believe you belong to any of the categories of protected veterans listed below, please indicate by making the appropriate selection.As a government contractor subject to the Vietnam Era Veterans Readjustment Assistance Act (VEVRAA), we request this information in order to measurethe effectiveness of the outreach and positive recruitment efforts we undertake pursuant to VEVRAA. Classification of protected categoriesis as follows:

A "disabled veteran" is one of the following: a veteran of the U.S. military, ground, naval or air service who is entitled to compensation (or who but for the receipt of military retired pay would be entitled to compensation) under laws administered by the Secretary of Veterans Affairs; or a person who was discharged or released from active duty because of a service-connected disability.

A "recently separated veteran" means any veteran during the three-year period beginning on the date of such veteran's discharge or release from active duty in the U.S. military, ground, naval, or air service.

An "active duty wartime or campaign badge veteran" means a veteran who served on active duty in the U.S. military, ground, naval, or air service during a war, or in a campaign or expedition for which a campaign badge has been authorized under the laws administered by the Department of Defense.

An "Armed forces service medal veteran" means a veteran who, while serving on active duty in the U.S. military, ground, naval or air service, participated in a United States military operation for which an Armed Forces service medal was awarded pursuant to Executive Order 12985.