Lead Engineer Design Verification

GreenWave Radios™; Bengaluru; On-site; INR 600,000 - 900,000; Full time

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Job summary

GreenWave Radios Bangalore is hiring a Lead Engineer - Design Verification to drive DV excellence for 5G products. You will verify ARM Cortex CPU subsystems and O-RAN blocks, build reusable UVM components, and collaborate across firmware, RTL, and system engineering.

Responsibilities include developing testbenches, integrating Python/C++ references, and advancing constrained-random verification, coverage, and regression strategies in a fast-paced environment.

Qualifications

• 8+ years in design verification with constrained-random and coverage-based methods.
• Proficient in SystemVerilog/UVM, C/C++, and verification planning.
• Experience with ARM Cortex subsystems, PCIe/Ethernet, and AMBA protocols.
• Strong debugging, waveform analysis, and regression management skills.

Responsibilities

• Verify ARM Cortex CPU subsystems and O-RAN packet processing blocks using Python reference models.
• Develop and maintain SystemVerilog/UVM testbenches with constrained-random testing.
• Create SoC-level verification environments and reusable components (drivers, monitors, agents).
• Integrate Python/C++ models with UVM; collaborate with firmware and RTL teams.
• Plan verification activities, execute tests, analyze coverage, and drive closure.
• Support emulation/FPGA prototyping and automation of regression flows.

Skills

SystemVerilog

UVM

C/C++

Python

Constrained-random verification

Debugging

Education

Engineering degree (EC/EE/CS)

Tools

Cadence vManager

Git

JIRA

Job description

InnoPhase Inc., DBA GreenWave Radios™, is at the forefront of innovation in Open RAN digital radios. Our cutting-edge solutions, powered by the Hermes64 RF SoC, are designed to enhance network energy efficiency while dramatically reducing operational expenses, with purpose-built silicon that is the heart of ORAN-based active antenna arrays.

Headquartered in San Diego, California, GreenWave Radios™ has established itself as a pioneer in delivering power-efficient digital-to-RF solutions. The company is supported by a talented team of over 100 engineers spread across four global R&D facilities. With an extensive portfolio of more than 120 global patents, GreenWave Radios™ continues to push the boundaries of radio technology and innovation.

InnoPhase Inc., DBA GreenWave™ Radios and Synergic Emergence have a co-employment relationship. For over three years, GreenWave Radios has partnered with Synergic Emergence, a professional employment organization provider, to offer our employees the best benefits and services. This arrangement means that Synergic Emergence provides employee pay checks and benefits, and GreenWave Radios will provide employment, evaluation, and advancement. By outsourcing some HR functions, GreenWave Radios can focus on what we do best – developing and implementing highly innovative SOC cellular radio integrated circuit products.

Job Description

InnoPhase Inc., DBA GreenWave™ Radios Bangalore is looking for a Lead Engineer - Design Verification to join our fast-paced and motivated team to drive excellence in our 5G products. This role is an excellent opportunity for someone that enjoys driving the critical path and making a significant impact in launching products into the market and winning!

Key Responsibilities

• Work as part of the Design Verification (DV) team to verify ARM Cortex-based CPU subsystems and/or O-RAN Packet Processer blocks using internally developed Python reference models.
• Work on verification of high-speed interfaces, including PCIe, Ethernet and other SerDes-based interfaces.
• Develop, maintain, and execute SystemVerilog/UVM-based testbench environments to verify RTL designs with bit-accurate and cycle-accurate reference models.
• Develop SoC-level verification environments, reusing verification components developed at IPs/ Subsystem and supporting constrained-random and directed testing, stimulus generation, and integration of custom and off the shelf VIP/UVCs.
• Verify ARM Cortex-based CPU subsystems, including CPU-to-peripheral communication, memory-mapped register accesses, interconnects, interrupt handling, and CPU interactions with hardware accelerators and networking blocks.
• Develop and execute comprehensive verification plans based on design specifications, collaborating closely with architects, RTL designers, firmware engineers, and cross-functional teams.
• Develop hardware/software (HW/SW) co-verification environments, including testbenches, use cases, APIs, and sequences; execute and debug software-driven verification scenarios.
• Integrate Python/C++ reference models with UVM environments and develop reusable verification components, including drivers, monitors, agents, scoreboards, predictors, and protocol checkers.
• Apply constrained-random verification, functional and code coverage, assertions, and regression testing to identify design issues and achieve verification coverage closure.
• Collaborate with firmware (FW) teams to transition DV sequences and test scenarios into firmware drivers and software-driven validation flows.
• Support hardware emulation, FPGA prototyping, and hardware-assisted verification activities.
• Develop and maintain automated verification and regression flows using Python, Perl, Tcl, and Shell scripting.
• Contribute to advanced verification methodologies, including transaction-level modelling (TLM), emulation/acceleration, and software-driven verification.

Job Requirements

• Bachelor's and/or Master's degree in Engineering (or equivalent) in EC/EE/CS.
• 8+ years of experience in design verification with strong expertise in constrained-random verification, functional and code coverage, assertion-based verification, gate-level simulation (GLS), and reference-model-based verification.
• Proven expertise in developing and verifying IPs, subsystem, and SoC-level designs using SystemVerilog, C/C++ and UVM.
• Strong hands-on experience integrating Python/C++ reference models into SystemVerilog/UVM environments, including developing agents, scoreboards, predictors, and reusable verification components for networking and packet-processing blocks.
• Experience in verifying O-RAN based packet processing systems and/or ARM Cortex-based CPU subsystems including memory-mapped interfaces, interconnects, interrupts, and hardware/software co-verification.
• Hands-on experience with on-chip interconnect protocols, particularly AMBA AXI/ AHB, as well as high-speed interfaces and communication protocols, including PCIe, Ethernet, and SerDes.
• Strong understanding of digital design verification methodologies and the complete verification lifecycle, including test planning, testbench development, test execution, debug, regression, and coverage closure.
• Proficiency in SystemVerilog, Verilog, UVM, and C/C++, along with scripting languages such as Python, Perl, Tcl, and Shell.
• Experience with Cadence vManager for verification metrics extraction, regression management, coverage analysis, and coverage closure.
• Strong debugging and problem-solving skills, including waveform analysis, assertion-based verification, functional coverage, and code coverage analysis.
• Experience with Git for version control, JIRA for issue tracking, and standard documentation and productivity tools.
• Strong communication and collaboration skills, with the ability to work effectively across design, verification, firmware, and system engineering teams.
• Competitive salary and stock options.
• Learning and development opportunities.
• Employer paid health Insurance.
• Earned, Casual, Sick & parental leaves.

Voluntary Self-Identification

For government reporting purposes, we ask candidates to respond to the below self-identification survey.Completion of the form is entirely voluntary. Whatever your decision, it will not be considered in the hiringprocess or thereafter. Any information that you do provide will be recorded and maintained in a confenical file.

As set forth in GreenWave Radios™’s Equal Employment Opportunity policy,we do not discriminate on the basis of any protected group status under any applicable law.

If you believe you belong to any of the categories of protected veterans listed below, please indicate by making the appropriate selection.As a government contractor subject to the Vietnam Era Veterans Readjustment Assistance Act (VEVRAA), we request this information in order to measurethe effectiveness of the outreach and positive recruitment efforts we undertake pursuant to VEVRAA. Classification of protected categoriesis as follows:

A "disabled veteran" is one of the following: a veteran of the U.S. military, ground, naval or air service who is entitled to compensation (or who but for the receipt of military retired pay would be entitled to compensation) under laws administered by the Secretary of Veterans Affairs; or a person who was discharged or released from active duty because of a service-connected disability.

A "recently separated veteran" means any veteran during the three-year period beginning on the date of such veteran's discharge or release from active duty in the U.S. military, ground, naval, or air service.

An "active duty wartime or campaign badge veteran" means a veteran who served on active duty in the U.S. military, ground, naval or air service during a war, or in a campaign or expedition for which a campaign badge has been authorized under the laws administered by the Department of Defense.

An "Armed forces service medal veteran" means a veteran who, while serving on active duty in the U.S. military, ground, naval or air service, participated in a United States military operation for which an Armed Forces service medal was awarded pursuant to Executive Order 12985.