Senior Design Engineer - Memory Subsystem

NVIDIA Gruppe; Bengaluru; On-site; INR 1,500,000 - 2,500,000; Full time

Job summary

NVIDIA Gruppe is seeking a Senior Design Engineer based in Bengaluru, India. In this role, you will be responsible for micro-architecture and RTL development for NVIDIA's advanced memory subsystem and interconnect IP. You'll work with cross-functional teams to ensure design correctness, perform post-silicon debugging, and meet critical design requirements.

Ideal candidates will have at least 4 years of design experience, a strong background in ASIC design flow, and expertise in Verilog. Join a diverse team that values equal opportunity!

Qualifications

• 4+ years of design experience required.
• Experience in micro-architecture and RTL development of complex designs.
• Deep understanding of ASIC design flow required.

Responsibilities

• Own micro-architecture and RTL development of design modules.
• Implement micro-architectural features to meet performance requirements.
• Collaborate with verification teams to ensure correctness of features.

Skills

Micro-architecture and RTL development

Verification teams collaboration

Problem-solving skills

Scripting knowledge (Python/Perl/shell)

Education

BS/MS or equivalent experience

Tools

VCS

Debussy

GDB

Job description

Senior Design Engineer – responsible for micro‑architecture, RTL development, verification, and post‑silicon debugging within NVIDIA’s state‑of‑the‑art memory subsystem and interconnect IP.

Responsibilities

• Own micro‑architecture and RTL development of design modules.
• Implement micro‑architectural features to meet performance, power, and area requirements.
• Work with hardware architects to define critical features.
• Collaborate with verification teams to verify the correctness of implemented features.
• Interact with timing, VLSI, and physical‑design teams to ensure the design meets timing, interface requirements, and is routable.
• Co‑operate with FPGA and software teams to prototype the design and ensure the software is tested.
• Work on post‑silicon verification and debugging.

Qualifications

• BS/MS or equivalent experience.
• 4+ years of design experience.
• Experience in micro‑architecture and RTL development of complex designs.
• Exposure to design and verification tools (e.g., VCS, Debussy, GDB).
• Deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, timing analysis, floor‑planning, ECO, bring‑up and lab debugging.
• Expertise in Verilog.

Preferred Skills

• Design experience in memory subsystem or network interconnect IP.
• Strong debugging and problem‑solving skills.
• Knowledge of scripting (Python/Perl/shell).
• Good interpersonal skills and a desire to work as part of a team.

We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.