Senior CPU Timing Engineer

Intel Technology India Pvt Ltd; Bengaluru; Híbrido; INR 1.200.000 - 1.800.000; Jornada completa

Descripción de la vacante

Intel Technology India Pvt Ltd in Bengaluru is seeking a CPU Senior Timing Engineer to drive top-level timing analysis and closure for CPU IP across implementation and signoff. You will develop constraints, MMMC scenarios and timing exceptions, collaborate with RTL, physical design and clock teams, and create automation scripts to improve timing closure efficiency in a hybrid work setup.

You will optimize timing across multiple corners and modes to meet frequency targets and support tapeout

Formación

• Bachelor's degree in Electrical/Electronics Engineering or related field with 4+ years hands-on experience OR Master's degree with 3+ years experience in CPU/high-performance IP timing closure
• Strong knowledge of static timing analysis, MMMC flows, timing constraints, OCV/derates, crosstalk and timing exceptions
• Hands-on experience with STA tools such as PrimeTime or Tempus, and familiarity with ICC2 or Innovus
• Proficiency in Tcl and at least one scripting language such as Python, Perl, or shell
• Strong debugging, problem-solving, and cross-functional communication skills

Responsabilidades

• Drive top-level timing analysis and closure for CPU IP across implementation and signoff stages
• Develop, review, and maintain timing constraints, MMMC scenarios, path budgets, and timing exceptions for top-level integration
• Analyze and resolve setup, hold, clock gating, noise, and cross-block timing issues affecting CPU performance targets
• Partner with RTL, block owners, physical design, and clock teams to close critical paths and improve timing convergence
• Ensure correlation between block-level, top-level, and signoff timing environments, and track timing risks against project milestones
• Develop scripts and methodology improvements to automate timing analysis, reporting, and closure efficiency

Conocimientos

Static timing analysis

STA tools

Scripting (Python/Tcl)

Cross-functional comms

Problem solving

Educación

Bachelor's degree in Electrical/Electronics Engineering or related field

Herramientas

PrimeTime

Tempus

ICC2

Innovus

Descripción del empleo

CPU Senior Timing Engineer Job Details: Job Description: The Role and Impact As a CPU Senior Engineer, you will play a pivotal role in shaping the future of high-performance computing by driving the physical design implementation of cutting‑edge CPU designs. You will ensure that the design meets frequency, power, and signoff targets across all required modes and corners. This role works across design, block timing, physical design, clocking, and integration teams to resolve critical timing issues, improve timing predictability, and support successful tapeout.

Business group You will join Intel Corporation's CPU design and development team, which is dedicated to engineering world‑class computing solutions. This group is at the heart of innovation, delivering high-performance designs that power industry‑leading technologies and support Intel's broader mission to advance computing performance and capabilities globally.

Key Responsibilities

• Drive top-level timing analysis and closure for CPU IP across implementation and signoff stages.
• Develop, review, and maintain timing constraints, MMMC scenarios, path budgets, and timing exceptions for top-level integration.
• Analyze and resolve setup, hold, clock gating, noise, and cross-block timing issues affecting CPU performance targets.
• Partner with RTL, block owners, physical design, and clock teams to close critical paths and improve timing convergence.
• Ensure correlation between block-level, top-level, and signoff timing environments, and track timing risks against project milestones.
• Develop scripts and methodology improvements to automate timing analysis, reporting, and closure efficiency.

Qualifications

Minimum Qualifications

• Bachelor's degree in Electrical Engineering, Electronics Engineering, or related field with 4+ years of hands‑on experience OR Master's degree in a relevant field with 3+ years of hands‑on experience with strong exposure to CPU or high‑performance IP timing closure.
• Strong knowledge of static timing analysis, MMMC flows, timing constraints, OCV/derates, crosstalk, and timing exceptions.
• Hands‑on experience with STA tools such as PrimeTime or Tempus, and familiarity with implementation tools such as ICC2 or Innovus.
• Proficiency in Tcl and at least one scripting language such as Python, Perl, or shell.
• Strong debugging, problem‑solving, and cross‑functional communication skills.

Preferred Qualifications

• Knowledge of scripting languages like Tcl, Perl, or Python for workflow automation in physical design.
• Proven ability to work effectively in dynamic, cross‑geographical, and interdisciplinary teams.
• Enthusiasm for designing world‑class CPUs that drive innovation and empower future technologies.

We're eager to welcome talented engineers who are passionate about technology and thrive in collaborative environments.

Job Type: Experienced Hire

Shift: Shift 1 (India)

Primary Location: India, Bangalore

Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust N/A

Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on‑site at their assigned Intel site and off‑site.

Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices.