Senior Technical Lead - CPU Physical Design

Intel Corporation; India; Hybrid; INR 4,500,000 - 6,000,000; Full time

Benefits offered by this job

Hybrid work model

Job summary

Intel Corporation in India, Bangalore, seeks a Senior Technical Lead - CPU Physical Design to guide physical implementation of next‑gen CPU IPs from floorplanning through signoff. You will provide technical leadership across the design lifecycle to achieve aggressive frequency, power, and area targets.

You will collaborate with Architecture, RTL, CAD, and Signoff teams, drive methodology improvements, mentor engineers, and shape efficient automation and AI‑driven workflows for design convergence

Qualifications

• 14+ years of industry experience in ASIC or CPU Physical Design.
• Expertise in floorplanning, design planning, placement and optimization.
• Strong mastery of timing closure, power integrity and signoff processes.

Responsibilities

• Lead physical design execution for CPU IPs from design planning through signoff.
• Provide technical leadership for floorplanning, placement, clock tree, routing, and verification.
• Drive PPA convergence and aggressive frequency, power and area targets.
• Partner with Architecture, RTL, CAD, Power, and Signoff teams to ensure success.
• Mentor engineers and drive automation and AI-driven design workflows.

Skills

Floorplanning

Placement & Optimization

Clock Tree Synthesis

Routing & Physical Verification

Timing Closure (STA)

PPA Optimization

Scripting (Python, Tcl, Shell)

Leadership & Mentoring

Education

M.Tech/MS/PhD in Electrical Engineering or related

Tools

Synopsys Fusion Compiler

ICC2

Cadence Innovus

PrimeTime

StarRC

Calibre

RedHawk

Job description

Job Details: Job Description: We are seeking a highly experienced and motivated Senior Technical Lead - CPU Physical Design to lead the physical implementation of next-generation CPU IPs from floorplanning through signoff. The successful candidate will provide technical leadership across the physical design lifecycle, driving PPA optimization, execution excellence, methodology adoption, and design convergence for high-performance CPU products. The ideal candidate brings deep expertise in advanced-node physical design, strong technical leadership, and a proven track record of delivering complex CPU, SoC, or high-performance IP designs.

Key Responsibilities

• Lead physical design execution for CPU IPs from design planning through signoff.
• Provide technical leadership for: Floorplanning and Design Planning Placement and Optimization Clock Tree Synthesis Routing and Physical Verification Timing Closure Power and Area Optimization Signoff Readiness Drive PPA convergence and deliver aggressive frequency, power, and area targets.
• Define and execute physical design strategies for advanced CPU architectures and technology nodes.
• Partner closely with Architecture, RTL, Circuit Design, DFT, CAD, Power, and Signoff teams to drive implementation success.
• Lead resolution of complex implementation, timing, congestion, and power challenges.
• Drive methodology improvements and adoption of best practice across multiple projects.
• Evaluate implementation tradeoffs and provide technical recommendations that influence architecture and design decisions.
• Mentor and guide engineers across the physical design organization.
• Collaborate with CAD teams to improve efficiency through automation, methodology enhancements, and AI-driven workflows.
• Support planning, estimation, risk assessment, and execution tracking for physical design deliverables.
• Contribute to hiring, technical interviews, and development of engineering talent.

Minimum Qualifications

• M.Tech/MS/PhD in Electrical Engineering, Computer Engineering, VLSI, or a related discipline.
• 14+ years of industry experience in ASIC or CPU Physical Design.
• Proven experience delivering successful products through complete physical implementation and signoff cycles.
• Strong expertise in: Floorplanning and Design Planning Placement and Optimization Clock Tree Synthesis Routing and Closure Static Timing Analysis Signal Integrity Power Integrity and EM/IR Physical Verification.
• Hands-on experience with industry-standard implementation tools such as: Synopsys Fusion Compiler ICC2 Cadence Innovus PrimeTime StarRC RedHawk Calibre.
• Strong scripting and automation experience using: Python Tcl Shell.

Preferred Qualifications

• Experience delivering high-performance CPU core, cache, fabric, or compute IP designs.
• Experience with advanced process technologies such as Intel 18A/14A, TSMC N3/N2, or equivalent.
• Deep understanding of: Physical design methodologies Advanced timing closure techniques Hierarchical implementation Variation-aware design methodologies Power-aware implementation.
• Experience leading geographically distributed teams.
• Experience driving CAD methodology improvements and automation initiatives.
• Familiarity with AI, Machine Learning, and Agentic AI applications for design automation and productivity enhancement.

Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations:

Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation or any other characteristic protected by local law, regulation or ordinance.

Position of Trust N/A

Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Job posting details (such as work model, location or time type) are subject to change. ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter. Intel’s official careers website.

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