CPU Clock Design Lead Engineer

Intel Technology India Pvt Ltd; Bengaluru; Hybrid; INR 3,500,000 - 6,000,000; Full time

Job summary

Intel Corporation in Bengaluru is seeking a CPU Clock Design Lead to drive clock distribution networks and CTS methodologies across high-performance CPU/SoC designs. The role blends design, analysis, and optimization to meet performance and power goals within a hybrid work model.

The candidate will perform timing analysis, develop clock solutions, and collaborate with architecture, design, and EDA teams to deliver scalable CPU technology. Shift 1 in India, experienced hire.

Qualifications

• Bachelor's degree in Electrical/Electronics or related field with 6+ years of hands-on experience in physical design implementation or Master's with 4+ years or PhD with 2+ years.
• Proficiency with CTS techniques using Synopsys and Cadence platforms.
• Experience in timing signoff, formal verification, and low-power design techniques.
• Understanding of submicron process node technologies and LVS/DRC methods.

Responsibilities

• Design, implement, and optimize clock distribution networks for CPU and SoC products.
• Contribute to clock architecture development and CTS methodologies.
• Perform timing analysis and support timing closure across complex designs.
• Develop custom circuits and clock-related design solutions.
• Assess performance, power, area, and timing tradeoffs to improve efficiency.
• Create automation using scripting and programming to boost productivity.
• Collaborate with architecture, design, physical implementation, validation, and EDA teams.
• Support debug, validation, and optimization throughout the product lifecycle.
• Drive issues to closure while maintaining high-quality engineering standards.
• Influence future methodologies and clocking technologies.

Skills

Clock design

Clock tree synthesis

Timing analysis

Problem solving

Communication

Education

Bachelor's degree in Electrical/Electronics

Master's degree in Electrical/Electronics

PhD in Electrical/Electronics

Tools

Synopsys

Cadence

Job description

CPU Clock Design Lead Job Details: Job Description: The Role and Impact

Join a Team That Defines the Heartbeat of Next-Generation CPUs. As a CPU Clock Design lead, you will contribute to the design, implementation, analysis, and optimization of clock distribution networks that enable industry-leading performance, power efficiency, and product scalability.

Business group: You will be part of Intel Corporation, joining a dynamic team dedicated to designing high-performance CPUs that drive Intel's leadership in the semiconductor industry. This group focuses on delivering cutting-edge solutions that support Intel's mission of creating world-changing technologies to enrich lives. Collaborating across multiple domains, the team enables groundbreaking designs that align with Intel's broader goals of innovation and excellence.

Key Responsibilities

• Design, implement, and optimize clock distribution networks for high-performance CPU and SoC products.
• Contribute to clock architecture development and clock tree synthesis (CTS) methodologies.
• Perform timing analysis and support timing closure across complex semiconductor designs.
• Develop custom circuits, library cells, and clock-related design solutions.
• Analyze performance, power, area, and timing tradeoffs to improve product efficiency.
• Create automation solutions using scripting and programming languages to improve design productivity.
• Collaborate closely with architecture, design, physical implementation, validation, and EDA teams.
• Support debug, validation, and optimization activities throughout the product development lifecycle.
• Drive technical issues to closure while maintaining high-quality engineering standards.
• Influence future methodologies, design flows, and clocking technologies.

Minimum Qualifications

• Bachelor's degree in Electrical, Electronics, or relevant field and 6+ years of hands-on experience in physical design implementation OR Master's degree in Electrical, Electronics, or relevant field with 4+ years of experience OR PhD with at least 2 years of experience in domain.
• Proficiency in clock tree synthesis (CTS) techniques and methodologies using Synopsys and Cadence platforms.
• Extensive experience in timing signoff, formal verification, and low-power design techniques.
• Strong understanding of submicron process node technologies and layout verification methods such as LVS/DRC.

Preferred Qualifications

• Strong ownership and accountability for technical deliverables.
• Curiosity and passion for solving complex engineering challenges.
• Effective problem-solving and analytical thinking skills.
• Ability to collaborate across multiple engineering disciplines.
• Strong communication skills with both technical and non-technical stakeholders.
• Adaptability and willingness to learn new tools, technologies, and methodologies.
• Ability to balance multiple priorities in a fast-paced environment.
• Continuous focus on quality, execution, and innovation.

Make an impact in shaping the future of CPU technology. Join us and be part of a world-class team that drives innovation and technological excellence at Intel.

Job Type: Experienced Hire

Shift: Shift 1 (India)

Primary Location: India, Bangalore

Additional Locations:

Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust: N/A

Work Model for this Role: This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

* Job posting details (such as work model, location or time type) are subject to change.

* ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.