Senior ASIC / RTL / Logic Design Engineer

Mulya Technologies; Hyderabad; On-site; INR 2,500,000 - 3,500,000; Full time

Job summary

A leading semiconductor firm is seeking a highly experienced Senior ASIC/RTL/Logic Design Engineer to join their Memory Controller Design Centre. This role requires extensive experience in ASIC design, specifically for high-performance memory controller IP catering to AI workloads. The ideal candidate will have substantial experience with Verilog/SystemVerilog and a strong grasp of digital design, alongside the ability to work collaboratively in a fast-paced environment. This position is based in Hyderabad, with the potential for relocation to Bangalore.

Qualifications

• 10+ years of hands-on experience in ASIC design and RTL development.
• Strong expertise in Verilog and SystemVerilog.
• Experience in using EDA tools for automation and scripting in Python, Perl, or TCL.

Responsibilities

• Design and deliver production-ready IP blocks for advanced memory controllers.
• Develop architecture and design specifications for AI compute workloads.
• Mentor junior engineers and drive continuous improvement in design quality.

Skills

Verilog

SystemVerilog

Digital design fundamentals

Memory subsystems

High-speed interfaces

Debugging skills

Problem-solving skills

Cross-functional collaboration

Education

B.E / M.Tech / Ph.D. in Electrical Engineering, Electronics, VLSI

Tools

Synopsys

Cadence

Mentor

Job description

Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore

Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market.

• Senior ASIC / RTL / Logic Design Engineer – Memory Controller Design – 1 position preferred in Hyderabad but can be accommodated in Blr too in case of constraints.

We are seeking a highly experienced, innovative, and technically strong ASIC / RTL / Logic Design Engineer to join our Memory Controller Design Centre of Excellence (CoE). This role offers the opportunity to architect and implement high‑performance memory controller IP for cutting‑edge AI compute platforms powering large‑scale data centers and advanced machine‑learning workloads.

Responsibilities

• Design and deliver standards‑compliant, production‑ready IP blocks for DDR5, HBM4, and LPDDR6 memory controllers, optimized for AI‑centric server SoCs operating at 9600 Mbps to 14400 Mbps and beyond.
• Develop architecture, micro‑architecture, and detailed design specifications tailored for AI compute workloads, ensuring best‑in‑class performance, power efficiency, and area (PPA).
• Enhance ASIC development flows using advanced EDA tools, automation, and scripting (Python, Perl, TCL) to support rapid iteration cycles for AI‑focused silicon.
• Implement complex RTL design blocks in Verilog/SystemVerilog, following robust design methodologies suitable for high‑bandwidth, low‑latency AI accelerators.
• Perform functional simulation, performance modeling, and debug to validate correctness and throughput under AI‑oriented traffic patterns.
• Demonstrate strong understanding of Lint, CDC, Synthesis, Power Analysis, STA constraints, and LEC for high‑frequency, high‑reliability server‑class designs.
• Define and optimize timing constraints to meet aggressive frequency targets typical of AI compute architectures.
• Identify, track, and resolve design bugs across the development lifecycle using industry‑standard tracking systems.
• Collaborate closely with verification, physical design, architecture, and firmware teams to ensure seamless integration into AI‑centric server chip platforms.
• Participate in design reviews, code reviews, and technical discussions, driving continuous improvement in design quality and methodology.
• Mentor junior engineers, fostering a culture of technical depth, innovation, and excellence.

Key Qualifications

• B.E / M.Tech / Ph.D. in Electrical Engineering, Electronics, VLSI, or related field from a reputed institution.
• 10+ years of hands‑on experience in ASIC design, RTL development, and logic design for complex SoCs or IP subsystems.
• Strong expertise in Verilog and SystemVerilog, with deep knowledge of digital design fundamentals, memory subsystems, and high‑speed interfaces.
• Proven experience with Lint, CDC, Synthesis, Power Analysis, STA, and LEC tools (Synopsys, Cadence, Mentor).
• Experience working on server‑class, high‑performance, or AI‑accelerator SoCs is a strong plus.
• Excellent analytical, debugging, and problem‑solving skills with the ability to thrive in a fast‑paced, product‑focused environment.
• Strong communication and collaboration skills for working with cross‑functional global engineering teams.