[India]Senior System-on-Chip Design Engineer

EdgeCortix Inc.; Bengaluru; On-site; INR 4,000,000 - 8,000,000; Full time

Benefits offered by this job

Competitive compensation package

Comprehensive PTO

Job summary

EdgeCortix Inc. is seeking a Senior SoC Engineer to drive RTL design, integration and related checks across frontend, DFT and verification. You will plan deliverables for one or more SOC subsystems and collaborate with verification, PD, and power teams to achieve production-quality silicon.

The role requires hands-on experience across design, clocking, low power, and IP evaluation, with a focus on solving complex architectural challenges in a fast-paced, collaborative environment.

Qualifications

• Experience in ASIC implementation flows including synthesis, timing, ECOs, STA and DFT/Power analyses.
• Hands-on involvement in Design for Test, clocking, low power design and PPA analysis.
• Ability to lead architectures discussions and mentor junior engineers.

Responsibilities

• Contribute to SOC RTL design, integration and verification checks.
• Own parts of SOC design including sub-systems and full-chip level design activities.
• Collaborate with verification, PD, DFT and power teams to reach production quality silicon.
• Mentor fresh engineers and drive cross-functional collaboration across Architecture, SOC and Implementation.

Skills

RTL design

Synthesis

Timing constraints

DFT/STA

Power management

RTL development

Cross-functional collaboration

Mentoring

Education

BTech / MTech / PhD in a relevant field

Tools

ARM Core Architecture

RISC-V

PowerPC

DDR

PCIe

ENET

UCIe

QSPI

I2C

USB

AXI/APB

Job description

Introduction

We are seeking a highly skilled Senior ASIC Implementation Engineer to join our team.

The successful candidate will be responsible for a range of key ASIC implementation tasks, including but not limited to synthesis, timing constraints, implementing ECOs, STA, Power intent implementation & validation, lint, power analysis, CDC RDC Analysis & Validation. You will also model and analyze performance, area, power, and system cost tradeoffs for different micro-architectures and contribute to implementation methodologies and flows.

Specific responsibilities will be a function of project and team needs and may vary over time. In addition to implementation tasks the successful candidate may also be asked to perform ASIC design tasks including some RTL development, or physical design activities from floor plan definition to P&R and participate in creative problem solving as part of a crossdisciplinary design team.

About Edgecortix

At Edgecortix we are a deep-tech startup revolutionizing edge computing with artificial intelligence and novel high efficiency silicon on chip design. Originating from multiple years of research, our unique AI hardware & software co-design principle and the Dynamic Neural Accelerator ® AI processor IP are geared towards positively disrupting the rapidly growing artificial intelligence edge hardware space and bring the power of AI and machine learning to all kinds of devices. Our operations are headquartered in Tokyo, Japan, with offices in Singapore, Virginia, California in the US. In addition, we are starting a new Design Center in India, located in Hyderabad.

The Team

As an engineering driven company we are working to define and solve the hardest problems in AI including computer vision, speech, and natural language, geared towards real-time capabilities on small to medium form factor devices. We originated out of multiple years of research, as such at our core we value learning, intellectual curiosity, and self-starters. We have the ambitious goal of enabling cloud-level performance with significantly better energy-efficiency for AI inference at the edge.

Role and Responsibilities

As the Senior SoC Engineer, you would be responsible for development and execution of SOC RTL Design, Integration, and related RTL design checks, participate and contribute to architecture discussions, work with DFT, Verification and Physical Design teams.

The role will involve owning parts of the SOC design (one or more subsystem, full-chip level design activities) and plan its deliverables in line with the overall project deliverables. Role requires hands-on-experience in all aspects and stages of Design, frontend, DFT, and Verification. Chip level aspects like Clocking, Booting, Low power design. PPA analysis, IP evaluations and selection are integral part of the job scope. Engagement and collaboration across the global teams is a key aspect of this role. Strong technical, analytical skills combined with strong communication, and consensus building skills are required. Senior SoC Engineer will partner with other design leads, architects and adhere to the best practices across all teams. A zero-defect, total quality mindset is a key enabler.

Responsibilities

• Key contributions to the SOC design and integration and all quality checks.
• Ownership, as applicable of the PPA, design constraints, Lint/CDC and work with different functions like verification, PD, DFT, etc. to get to a production quality Silicon
• Train and mentor fresh engineers for increased productivity
• Build up strong collaboration with other R&D team members and leads across Architecture, SOC and Implementation,
• Influences technical strategy to drive innovation, e. g., products, technology and/or patents.

Requirements

• BTech /MTech/ PhD with 10+ years' experience in the semiconductor industry.
• Candidate should be an experienced team lead or technical manager having experience of leading a team in SoC Design and Verification.
• Experience in wireless standards and connectivity, including signal processing.
• Experience of SoCs based on ARM Core Architecture, RISC V, Power PC, etc.
• Understanding of high-speed peripherals like DDR, PCIe, ENET, UCIe
• Familiarity with Other interfaces like QSPI, I2C, USB
• memory subsystem architecture knowledge
• Knowledge of Neural Accelerators, CPUs, ARM subsystems, AXI/APB interfaces
• Strong domain knowledge of Clocking, System modes, Power management, debug, interconnect, security and other architectures
• Experience of working with Lint, CDC, RDC, Power Aware/Low power design.
• Power management understanding
• Continuous learning and improvement
• Pushing the envelope
• Chiplet implementation and understanding of System In Package. Knowledge of latest packaging/substrate technologies
• Die to Die interfaces knowledge.

What’s in it for you?

Make a difference: you will have the opportunity to join a well-funded fabless AI semiconductor startup that is disrupting the AI software and hardware co-design space. Be an integral part of its growth and momentum.

Benefits

• Competitive compensation package
• Comprehensive paid time off, vacations and sick leaves