RTL - FPGA Design Engineer

ACL Digital; Hyderabad; Sur place; INR 1 200 000 - 2 100 000; Plein temps

Résumé du poste

ACL Digital in Hyderabad seeks an FPGA engineer to own end-to-end Xilinx Vivado flows, including synthesis, implementation, XDC constraints, DRC and bitstream generation.

You will drive regression builds and automation scripts, collaborating with firmware and board teams for hardware bring-up and validation, and document interface specifications and register mappings.

Qualifications

• Experience with end-to-end FPGA design flows.
• Ability to document interfaces and register mappings.
• Hands-on with Xilinx Vivado tools and flows.

Responsabilités

• Own end-to-end Xilinx Vivado flows: synthesis, implementation, XDC, DRC, bitstream.
• Drive regression builds and automation scripting.
• Collaborate with firmware/board teams for hardware bring-up and validation.

Connaissances

Vivado flows

Synthesis

Implementation

XDC constraints

Regression automation

Hardware bring-up

Outils

Xilinx Vivado

FPGA

AXI

Description du poste

Take ownership of end-to-end Xilinx Vivado flows, including synthesis, implementation, XDC constraints, DRC, and bitstream generation.

Drive regression builds and automation scripting while collaborating with firmware and board teams for hardware bring-up and validation.

Bring strong hands-on expertise in AXI protocols, embedded I/O interfaces, register mapping, and comprehensive design documentation.