RTL Design Specialist - UFS/MMC/USB/PCIe /UCIe/I2C/I3C/SMBus/SPI/UART

Samsung Semiconductor India Research SSIR; Bengaluru; On-site; INR 4,500,000 - 6,500,000; Full time

Job summary

Samsung Semiconductor India Research (SSIR) in Bengaluru seeks a senior SoC/IP RTL Design Engineer to lead architectural definition and subsystem integration. You will drive PCIe/UCIe, NoC topology, and AMBA protocol compliance while coordinating across global teams for pre- and post-silicon validation.

The role demands 5–18 years in RTL design, strong timing and DFT experience, and a track record of delivering complex interconnects in cutting-edge SoCs.

Qualifications

• 5–18 years of experience in SoC/IP RTL design and subsystem architecture.
• Expertise in PCIe, UCIe, UFS, MMC, USB, AXI/AMBA, I2C/I3C/SMBus, SPI, UART.
• Strong knowledge of NoC concepts and timing/latency tuning.
• Experience with GLS closure, DFT/UPF checks, and high-frequency timing.
• Proven track record in RTL lint, CDC, and SDC constraints.

Responsibilities

• Architectural definition of subsystem structure and NoC for PCIe Gen 5/6/7 and UCIe.
• Ensure compliance with AMBA CHI/ACE/AXI for data movement.
• Lead interconnect IP integration into the SoC top-level with latency optimization.
• Drive timing, SDC constraints, Formality checks, and low-power verification.
• Collaborate across geographies on pre/post-silicon validation and debugging.

Skills

PCIe/UCIe

NoC design

RTL design

High-speed serial protocols

AMBA CHI/ACE/AXI

Low-power design UPF/VCLP

Verdi debugging

Education

Bachelor's/Master's in EE/CS

Tools

Verdi

Job description

About Samsung Semiconductor India Research (SSIR)

With a wide range of industry-leading semiconductor solutions, we are enabling innovative growth in market segments in component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, Storage Solutions, AI/ML, 5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more.

As one of the largest R&D centers outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products.

Subsystem & Protocol Experts with Focus on Architecture, High-level Integration, Bus Fabric, connectivity PCIe/ UCIe, NoC, and High-Bandwidth Protocols.

SoC Subsystem Design Engineer - High-Speed Interconnect (PCIe/UCIe) OR Storage & Peripheral Fabric (UFS/MMC/USB) OR Low-Speed Peripheral Fabric

Focus: Global connectivity PCIe/ UCIe, NoC, and High-Bandwidth Protocols.

Qualifications:

1. 5 18 years of experience in SoC/IP RTL Design and Subsystem Architecture.
2. Strong expertise in storage or high-speed peripheral protocols, including UFS, MMC, and USB (2.0/3.0/SS), PCIe and UCIe, I2C, I3C, SMBus, SPI, UART Etc
3. Sound knowledge of the complete AMBA protocol stack, specifically AXI, AHB, and APB.
4. Expert-level experience in low-power architecture design using UPF and VCLP.
5. Proven track record in managing GLS (Gate Level Simulation) closure and implementing Functional ECOs.Advanced expertise in high-speed serial protocols, specifically PCIe Gen 5/6/7 and UCIe specifications.
6. Sound knowledge of the complete AMBA protocol stack, with mastery of CHI, ACE, and AXI.
7. Proven experience in NoC (Network-on-Chip) concepts, interconnect topology, and performance/latency tuning.
8. Deep understanding of SDC constraints, STA Timing analysis, and high-frequency timing closure.
9. Strong grasp of RTL Lint, CDC, SDC constraints, and DFT checks for complex subsystems.

• Job Summary: Lead the architectural definition and subsystem-level integration
• Key Responsibilities:

1. Architectural Definition: Define the subsystem structure and NoC concepts for PCIe Gen 5/6/7 and UCIe ,. Create micro-architecture and Hardware Design Documents (HDD).
2. Protocol Mastery: Ensure strict compliance with AMBA CHI, ACE, and AXI protocols for high-performance data movement.
3. System Integration: Manage the integration of interconnect IPs into the SoC top-level, focusing on latency tuning and bandwidth optimization.
4. Quality & Timing: Drive SDC constraints, STA Timing analysis, and Formality checks at the subsystem level.
5. Validation & Collab: Lead pre- and post-silicon validation and work collaboratively with global SoC teams across various geographies.
6. Flows: Oversee RTL Lint, CDC, UPF/VCLP low-power checks, and DFT checks. Use Verdi for system-level debugging.

• Qualifications:

5–18 years of experience in SoC/IP RTL Design and Subsystem Architecture.

Advanced expertise in high-speed serial protocols, specifically PCIe Gen 5/6/7 , UCIe , UFS, MMC,USB ,PCIe and UCIe, I2C, I3C, SMBus, SPI, UART Etc specifications.

Sound knowledge of the complete AMBA protocol stack, with mastery of CHI, ACE, and AXI.

Proven experience in NoC (Network-on-Chip) concepts, interconnect topology, and performance/latency tuning.

Deep understanding of SDC constraints, STA Timing analysis, and high-frequency timing closure.

Experience in driving system-level RTL Lint, CDC, Formality, and Low-power checks (UPF, VCLP).

Disclaimer

Samsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.

Confidentiality Notice: Candidates are reminded that all proprietary information, trade secrets or confidential materials belonging to or obtained from their past or current employers must not be shared or used in connection with their application, interviews, or future employment with our organization

• Seniority Level
  Mid-Senior level