RTL Design Manager

AMD; Hyderabad; On-site; INR 4,000,000 - 7,000,000; Full time

Benefits offered by this job

Benefits described: AMD benefits at a‑

AMD benefits at a glance

Job summary

AMD Hyderabad is seeking a capable SOC Design Manager to lead the Front End SOC Design Team for next-gen Adaptable Compute Acceleration Platform devices. You will guide RTL design, IP integration, and DFT flows, coordinating with cross-functional teams across time zones to deliver high-performance, low-power SOCs.

The role requires extensive hands-on design leadership, strong communication, and a track record of managing silicon projects from microarchitecture through timing closure.

Qualifications

• Bachelors or Masters in Electrical Engineering with 12+ years of experience.
• Experience with RTL design in Verilog/SystemVerilog.
• Solid understanding of DFT technologies and DFT flows.
• Experience with SOC tools: Spyglass, Questa CDC, Cadence Conformal, VCS.
• Knowledge of timing constraints across multiple clock domains.
• Experience with UPF power intent and design islands.
• Scripting with TCL, Python, Perl; version control with Perforce/Git.
• Fluent in Linux and Windows environments.

Responsibilities

• Lead and manage SOC design team, hiring and coaching engineers.
• Plan projects, track execution, and report key metrics.
• Oversee design reviews for features and quality.
• Drive tapeout processes and post-tapeout checks.
• Improve design methodologies, incorporate AI/automation.

Job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them.

AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward.

THE ROLE:

• AMD is seeking a capable and motivatedSOC Design Manager to be part of Front End SOC Design Team of next generation Adaptable Compute Acceleration Platform devices
• You will manage team working on design and implementation of high-performance, low-power SOCs and SOC Chiplets targeting a wide range of applications as well as customer specific products
• This high visibility and critical role will require technical leadership in developing microarchitecture, implementing functions in RTL, integrating IP from internal and external sources, ensuring quality and getting design ready for synthesis.
• You will also contribute to definition/evolution of IP/SOC Design methodologies and processes for future projects

THE PERSON:

• Successful candidate will have an SOC/ASIC Design background, team/project management experience, would have participated in several silicon design projects with increasing level of scope/responsibilities and has a history of achieving results through effective execution

KEY RESPONISIBILITES:

• Team management (hiring, coaching, reviewing and retaining engineers)
• Project Planning
• Tracking Project Execution and reporting of key metrics
• Managing Design reviews around feature and quality
• Retrospectives and project wind-down
• Crossfunctional stakeholder management (marketing, architecture, verification, physical design, chip integration, applications, methodology experts, management)
• Participate in tapeout checklists and reviews
• Improve processes for team through AI adoption and traditional automation

REQUIRED EXPERIENCE:

• Engineering
  • Digital design and experience with RTL design in Verilog/System Verilog
  • Solid understanding of DFT technologies and some experience with execution of DFT flows
  • Experience with SOC tools including Spyglass, Questa CDC, Cadence Conformal, VCS simulation
  • Experience in specifying timing constraints with several clock domains and modes
  • Basic experience with Synopsys Design Compiler and Primetime
  • Experience designing with multiple power domains and islands using UPF
  • TCL, Python, Perl scripting
  • Version control systems such as Perforce, IC Manage or Git
  • Fluent in working with Linux and Windows environments
• Leadership/Management
  • Strong verbal and written communication skills
  • Ability to organize and presentcomplex technical information
  • Project planning and management of execution from Microarchitecture to Timing Closure with engineers in multiple timezones
  • Team building experience

Academic Credentials and Experience

• Bachelors or Masters degree in Electrical Engineering with 12+ years of experience.

#LI-PP2

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.