RISC-V System IP Design Lead

Qualcomm; Chennai District; On-site; INR 3,500,000 - 6,500,000; Full time

Job summary

Qualcomm India Private Limited seeks a senior Systems Engineer with 8+ years of IP/SoC design and micro-architecture expertise in Chennai. The role requires knowledge of RISC-V or ARM ISA and interconnect protocols (CHI, AHB/AXI/ACE), digital design and RTL development, and hands-on SoC design with Verilog RTL coding.

Candidates should understand CPU architecture, coherency and virtualization, and experience with synthesis, verification, silicon debugging, and front-end design tracking.

Qualifications

• 8+ years of solid experience in IP/SoC design and micro-architecture
• RISC-V ISA or ARM ISA knowledge
• Understanding of interconnect protocols like CHI/AHB/AXI/ACE/ACE-Lite/NoC concepts
• Good knowledge of Digital Design and RTL development
• Hands-on experience with SoC Design, Verilog RTL coding
• Understanding of CPU architecture, coherency protocols and virtualization.
• Working knowledge of Synthesis, DC/DCG synthesis with Synopsys design compiler, DFT, verification, formal verification, silicon debug
• Working knowledge of Lint, CDC, PLDRC, CLP etc
• Good understanding of the design convergence cycle in terms of architecture, micro-architecture, synthesis, timing closure and verification
• Manage SoC dependencies, planning and tracking of all front-end design related tasks
• Driving project milestones across the design, verification and physical implementations
• Should possess effective communication and leadership skills

Skills

SoC design

RTL development

Verilog

CPU architectures

Synthesis

Formal verification

Silicon debugging

Communication

Leadership

Education

Bachelor's in Engineering/CS/IS

Master's in Engineering/CS/IS

PhD in Engineering/CS/IS

Tools

Synopsys Design Compiler

DFT tooling

Lint

CDC

PLDRC

Job description

Company:

Qualcomm India Private Limited

Job Area:

Engineering Group, Engineering Group > Systems Engineering

General Summary:

• 8+ years of solid experience in IP/SoC design and micro-architecture
• RISC-V ISA or ARM ISA knowledge
• Understanding of interconnect protocols like CHI/AHB/AXI/ACE/ACE-Lite/NoC concepts
• Good knowledge of Digital Design and RTL development
• Hands-on experience with SoC Design, Verilog RTL coding
• Understanding of CPU architecture, coherency protocols and virtualization.
• Working knowledge of Synthesis, DC/DCG synthesis with Synopsys design complier, DFT, verification, formal verification, silicon debug
• Working knowledge of Lint, CDC, PLDRC, CLP etc
• Good understanding of the design convergence cycle in terms of architecture, micro-architecture, synthesis, timing closure and verification
• Manage SoC dependencies, planning and tracking of all front-end design related tasks
• Driving project milestones across the design, verification and physical implementations
• Should possess effective communication and leadership skills

Minimum Qualifications:

• Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 4+ years of Systems Engineering or related work experience.

OR
Master's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Systems Engineering or related work experience.

OR
PhD in Engineering, Information Systems, Computer Science, or related field and 2+ years of Systems Engineering or related work experience.

Minimum Qualifications:

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.

OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ year of Hardware Engineering or related work experience.

OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Applicants:

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