RFIC Layout Manager

MaxLinear; Bengaluru; On-site; INR 2,000,000 - 3,500,000; Full time

Job summary

MaxLinear is hiring a Senior Manager – RFIC Layout in Bengaluru, India. This role involves leading RF/Analog layout teams, ensuring high-quality delivery of design projects while mentoring team members. You will manage end-to-end layout development across product lines, collaborating with cross-functional teams.

The ideal candidate will have over 20 years of experience, strong leadership skills, and in-depth knowledge of RF signal path design. Excellent communication and mentoring capabilities are essential for success in this position.

Qualifications

• 20+ years of experience in RF/Analog layout management.
• Experience in managing and mentoring large teams of 20+ members.
• Proven expertise in layout development across product lines.

Responsibilities

• Lead and manage RF/Analog layout teams ensuring project delivery.
• Own end-to-end layout development with accountability.
• Provide technical leadership for RF signal path implementations.

Skills

RF/Analog layout management

Team mentorship

Technical leadership

Communication skills

Floor-planning for RF/Analog chips

Education

Tech/B.E. degree

Job description

Responsibilities

We are seeking an experienced and accomplished Senior Manager – RFIC Layout to lead and drive layout development for complex RF/Analog ICs. This role requires strong technical expertise, proven leadership capabilities, and the ability to manage large teams while owning end‑to‑end layout delivery across product lines. The ideal candidate will play a critical role in mentoring teams, enabling advanced technology adoption, and ensuring high‑quality execution in a cross‑functional environment.

• Lead and manage RF/Analog layout teams, ensuring high‑quality and timely delivery of design projects.
• Own end‑to‑end layout development across product lines with strong accountability.
• Mentor, train, and scale teams including freshers and contractors.
• Drive floor‑planning for complex RF/Analog chips and IPs considering noise and isolation constraints.
• Provide technical leadership in RF signal path and high‑speed design implementations.
• Collaborate with cross‑functional teams including ASIC, PnR, CAD, and Packaging.
• Ensure compliance with Analog IP deliverables, QC processes, and release flows.
• Enable team readiness for advanced technology nodes and evolving design challenges.

Qualifications

• Tech/B.E. with 20+ years of experience in RF/Analog layout.
• Experience in managing/mentoring large teams consisting of 20+ members.
• Strong communication skills with proven track record of owning layout development from product lines.
• Strong technical mentorship skills, ability to hire/training teams, train freshers/contractors.
• Floor‑planning experience for complex RF/Analog chips & IPs with magnetic coupling isolation constraints and noise isolation constraints.
• Experience in handling chipsets/top‑levels in Wireless/Wi‑Fi transceivers and proficiency with RF signal path building blocks such as LNA, mixers, RFPLLs, PA, multi‑GHz ADCs and DACs (added advantage).
• Experience with high‑speed Serdes designs (PAM4, PCIe, etc.) and hands‑on experience in building blocks of Serdes (CTLE, ADCs, DACs, PLL, high‑speed clock distribution, etc.).
• Good exposure to Fin‑FET technology challenges (5nm, 3nm) and ability to ramp up the team on new technology nodes.
• Good overview of the deliverables/QC of an Analog IP in SoC context and release flows.
• Strong cross‑functional knowledge/deliverables with teams such as ASIC, PnR, CAD and Packaging.
• Knowledge in ESD/IO design (added advantage).