RF Engineer

7RD; Delhi; Sur place; INR 1 500 000 - 2 400 000; Plein temps

Résumé du poste

7RD is building the Counter Drone Swarm Stack with an EdgeAI module for drones, requiring an experienced RF and signal processing engineer in Delhi. The role focuses on turning RF sensing requirements into a multi-receiver system for RF source localization using time difference of arrival (TDOA).

You will own signal chain design, low-latency DSP, FPGA firmware, and validation through lab and field tests. Responsibilities span SDR platform selection, digital signal processing, receiver

Qualifications

• Bachelor's degree in Electronics, Telecommunications, Electrical Engineering or related field.
• 3+ years hands-on SDR hardware and DSP algorithm experience.
• Real-time I/Q data acquisition and processing design.
• FPGA development including HDL for streaming datapaths.
• Knowledge of time synchronization and TDOA estimation.

Responsabilités

• SDR system design: select/configure SDR platforms, RF front ends, sampling rates, bandwidths, gains, filtering, and I/Q paths.
• Digital signal processing: develop detection, filtering, channelization, resampling, correlation, spectral estimation.
• Receiver synchronization: align distributed receivers with references; calibrate clock drift and timestamp offsets.
• TDOA localization: estimate time differences, resolve correlations, compute source position, report geometry limits.
• Real-time processing: build high-rate I/Q pipelines with buffering, latency control, and resource management.
• FPGA firmware: develop/validate FPGA logic for SDR paths, including capture, timestamping, filtering, decimation, DMA.
• System integration: connect receivers, FPGA, host software, networks, storage, and visualization.
• Test/calibration: use signal generators, known transmitters, I/Q data, and field tests; compare to ground truth.
• Engineering delivery: maintain schematics, code reviews, versioned builds, and documentation.
• Cross-functional support: work with RF hardware, embedded software, FPGA, and field-test teams.

Connaissances

C/C++

Python

DSP Algorithms

FPGA

RTOS

Formation

Bachelor's degree in Electronics/ECE

Outils

GNU Radio

UHD

SoapySDR

Linux

Description du poste

7RD is building the Counter Drone Swarm Stack, powered by our core product: an EdgeAI Module for drones, a neural chip based "brain" that runs autonomous mission planning, target tracking, and navigation entirely on the edge, with no cloud or GPS dependency.

Job Description

SignalProcessing, FPGA and RF Localization

Employment Type:

Full Time

Experience Level:

3+ Years

Department:

Engineering / RF and Signal Processing

RolePurpose

The engineerwill turn RF sensing requirements into a working multi receiver system thatdetects and localizes RF sources using time difference of arrival (TDOA). Theposition requires practical ownership from signal chain design and receiversynchronization through low latency DSP, FPGA firmware, source positionestimation, and verification through laboratory and field measurements.

KeyResponsibilities

• SDR system design: Select and configure SDR platforms, RF front ends, sampling rates,bandwidths, gain settings, filtering, and I/Q capture paths for the requiredsignals.
• Digital signalprocessing: Develop detection, filtering, channelization,resampling, correlation, spectral analysis, and signal quality estimationalgorithms.
• Receiver synchronization: Align distributed receivers with suitablefrequency and time references; characterize clock drift, timestamp uncertainty,calibration offsets, and transport delay.
• TDOA localization: Estimate time differences from captured signals, resolve ambiguouscorrelations, solve for source position, and report confidence and geometryrelated limits.
• Real time processing: Build efficient streaming pipelines for high rate I/Q data withcontrolled buffering, loss detection, latency, memory use, and CPU oraccelerator load.
• FPGA firmware: Develop and validate FPGA logic for SDR data paths, including samplecapture, timestamping, digital downconversion, filtering, decimation, DMA, andhost interfaces.
• System integration: Connect receivers, FPGA logic, host software, networking, timingsources, storage, visualization, and control interfaces into a reliable sensingsystem.
• Test and calibration: Create repeatable tests using signal generators, known transmitters,recorded I/Q data, simulation, and field measurements; compare estimates withground truth.
• Engineering delivery: Maintain schematics and interface assumptions, code and HDL reviews,versioned builds, performance reports, calibration records, and releasedocumentation.
• Cross functional support: Work with RF hardware, embedded software,FPGA, and field test teams to trace errors across the complete signal andtiming path.

Requirements

CoreTechnical Areas

Expected Knowledge andApplication

Receiver noise figure, dynamic range, gain,filters, antennas, interference, propagation, multipath, and practicalspectrum measurement.

DSP

Complex sampling, Fourier analysis,filtering, decimation, detection thresholds, cross correlation, spectralestimation, and fixed point effects.

SDR platforms

RF transceiver configuration, I/Q streaming,sample formats, clocking, calibration, driver APIs, and recorded data replay.

Timing and sync

Shared references or disciplined clocks, PPSor equivalent timing, timestamp alignment, drift compensation, and errorbudget analysis.

Correlation peak selection, wideband delayestimation, outlier rejection, sensor geometry, multilateration, uncertainty,and performance under multipath.

Verilog, VHDL, or SystemVerilog; pipelinedDSP, timing closure, clock domain crossing, memory use, AXI or equivalentbuses, and simulation.

Real time software

C++ or C for low latency pipelines, Pythonfor analysis and tooling, concurrency, backpressure, profiling, and stabledata interfaces.

Verification

Signal generators, oscilloscopes, spectrumanalyzers, logic analyzers, FPGA test benches, I/Q datasets, and ground truthfield tests.

RequiredQualifications

• Bachelor's degree or equivalent practicalexperience in Electronics, Telecommunications, Electrical Engineering, SignalProcessing, Computer Engineering, or a closely related discipline.
• At least 3 years of hands on experience withSDR hardware and development of DSP algorithms for sampled RF signals.
• Experience designing or implementing real timeI/Q data acquisition and processing under bandwidth, latency, and computeconstraints.
• FPGA development experience, including HDLdesign, simulation, hardware debugging, and timing closure for streaming datapaths.
• Understanding of time synchronization and itseffect on TDOA estimation and RF source localization.
• Strong C or C++ programming ability, practicalPython for analysis and test automation, and disciplined use of Git andtechnical documentation.
• Ability to diagnose system errors across RFhardware, clocks, FPGA logic, software, networking, and measurement setup.

PreferredExperience

• Development of multi receiver TDOA,multilateration, direction finding, spectrum monitoring, or passive RF sensingsystems.
• Use of GNU Radio, UHD, SoapySDR, or vendor SDRSDKs; familiarity with Linux device interfaces and embedded deployment.
• DSP implementation on FPGA or SoC platforms,including digital downconversion, high throughput DMA, fixed pointoptimization, and hardware software partitioning.
• Experience with GNSS disciplined oscillators,PPS timing, PTP or other network time methods, and distributed sensorcalibration.
• Statistical estimation, tracking, confidencemetrics, sensor fusion, or robust localization in multipath and low signal tonoise conditions.
• Deployment of distributed RF systems in fieldconditions, including reliable networking, remote diagnostics, and repeatablecalibration procedures.