Radisys 5G gNB CU

Acldigital; Bengaluru; On-site; INR 3,000,000 - 5,500,000; Full time

Job summary

Acldigital seeks an experienced wireless engineer to design and implement CU‑L3 components for 5GNR networks in Bengaluru. You will work on CU‑CP/CU‑UP functionality and integrate with DU and core network simulators, applying strong C++ skills and robust debugging practices.

Ideal candidates have deep knowledge of 3GPP signaling, edge-case call flows, and the ability to optimize protocol stacks within Agile CI environments.

Qualifications

• Solid foundation in LTE and 5GNR wireless tech stacks with focus on L3/CU architectures.
• Deep knowledge of real-world 3GPP signaling and critical edge-case call flows.
• Proficient in C++ with clean OOP design and memory/thread issue tracking.

Responsibilities

• Design and implement CU‑CP OR CU‑UP functionality per 3GPP Rel‑15/16/17.
• Develop and optimize control plane protocols: RRC, NGAP, F1‑C, E1AP.
• Develop and optimize user plane handling: F1‑U, GTP‑U, QoS flows, bearer management, PDCP and SDAP.
• Integrate CU with DU, 5G Core (AMF/SMF/UPF), and USIM/UE simulators.
• Work in an Agile team framework, maintain version control, and deploy code via CI pipelines.

Skills

C++

L3/CU architectures

5G/LTE knowledge

RRC/NGAP/CU protocols

Debugging in hardware

Agile/CI

Job description

Design and implement CU‑CP OR CU‑UP functionality per 3GPP Rel‑15/16/17

Develop and enhance control plane protocols: RRC, NGAP, F1‑C,E1AP.

Develop and optimize user plane handling: F1‑U, GTP‑U, QoSflows, bearer management, PDCP and SDAP
Integrate CU with DU, 5G Core (AMF/SMF/UPF), and USIM/UE simulators.

We are looking for someonewho:

Is a wireless engineeringprofessional with a solid technical foundation in LTE and 5GNR wireless techstacks, explicitly focusing on L3/CU network architectures

Has high proficiency in C++with clean object-oriented design and a methodical approach to tracking memoryor thread issues

Possesses deep knowledge ofreal-world 3GPP signaling, critical edge-case call flows, and protocol layerlogic

Demonstrates excellentdiagnostic and debugging skills in hardware environments (x86/ARM)

Designing, developing, andscaling robust 5GNR L3/CU infrastructure components and contributing tolow-level designs

Working closely on complexprotocol layer stacks to optimize handling of RRC signaling and core interfaceflows

Diagnosing performanceconstraints, memory leaks, or thread optimizations within executionenvironments

Working inside an Agileteam framework, maintaining version control integrity, and deploying code usingstandard continuous integration pipelines