Principal Logic Design Engineer

844 Altera Semiconductor Technology India Pvt. Ltd.; New Delhi; Hybrid; INR 1,500,000 - 2,200,000; Full time

Job summary

844 Altera Semiconductor Technology India Pvt. Ltd. is seeking an experienced candidate for design development tasks in New Delhi. The role involves developing logic designs, RTL coding, and generating functional units for IP integration.

Ideal candidates should have 15+ years of experience in electrical or computer engineering, expertise in System Verilog and FPGA design, and proficiency in programming languages such as C/C++ and Python. This is a regular full-time position with remote work options available.

Qualifications

• 15+ years' experience with a bachelor’s or master’s degree in electrical engineering, computer engineering, or a related field.
• Experience in System Verilog, VCS/Synopsys simulators, Lint, and synthesis.
• Experience programming with C/C++/Perl/Python/TCL/Unix shell scripts.

Responsibilities

• Participate in design development tasks throughout the IP development flow.
• Develop the logic design, RTL coding, and simulation for an IP.
• Generate cell libraries, functional units, IP blocks, and subsystems for integration.

Skills

System Verilog

C/C++/Perl/Python/TCL

FPGA design and programming

RTL validation

Good communication skills

Problem-solving skills

Education

Bachelor’s or Master’s degree in Electrical Engineering or related field

Tools

VCS/Synopsys simulators

Lint and synthesis

Job description

Company Overview

Altera, a leader in programmable solutions from cloud to edge, delivers cutting‑edge FPGA, CPLD, and IP technologies. We are driving innovation in high‑speed connectivity, AI acceleration, and next‑generation data infrastructure. Our mission is to empower engineers to design and deploy advanced systems with unmatched flexibility and performance.

Key Responsibilities

1. Participate in design development tasks throughout the IP development flow.
2. Develop the logic design, register transfer level (RTL) coding, and simulation for an IP.
3. Generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs.
4. Apply various strategies, tools, and methods to write RTL and optimize the logic to meet the IP release requirement.
5. Involve in design example creation, simulation example creation, IP integration and release process.
6. Involve in IP design example brings up on hardware, hardware verification and failure debugging.

Qualifications

1. 15+ years' experience with a bachelor’s or master’s degree in electrical engineering, computer engineering, or a related field.
2. Experience in System Verilog, VCS/Synopsys simulators, Lint and synthesis.
3. Experience programming with C/C++/Perl/Python/TCL/Unix shell scripts.
4. Experience in FPGA design and programming is a plus.
5. Experience in RTL validation is a plus.
6. Ability to work with different teams, good communication and problem‑solving skills.

Job Details

Job Type: Regular. Shift: Shift1 (India). Primary Location: New Delhi, India (Remote). Additional Locations: Bengaluru, Karnataka, India.

EEO Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.