Principal Engineer Verification

Infineon Technologies; Hyderabad; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

Infineon Technologies in Hyderabad seeks a senior verification engineer to drive UVM-based validation of complex IC designs. You will develop testbenches, write SystemVerilog code, and collaborate with architects, designers and project managers to meet schedules.

Responsibilities include driving verification metrics, regression setups, and post-silicon validation support, while communicating across teams and with customers during design reviews.

Qualifications

• Bachelor’s in electrical engineering or equivalent.
• Proven expertise with UVM and/or SystemVerilog based verification.
• Excellent understanding of ASIC verification methodologies.
• Experience with source control tools and release management tools like Jenkins, Git, and Jira.

Responsibilities

• Performs and supervises detailed simulation, verification and validation of ICs.
• Develop testbenches using SystemVerilog and UVM for functional and power aware RTL.
• Develop UVM components such as agents, scoreboards, environment, assertions, and functional coverage.
• Develop test plans, UVM sequences, layered sequences, and virtual sequencers.
• Drive closure of verification metrics to cover verification space; identify and close gaps in functional, power aware and gate level timing simulation.
• Provide regression setup and debug of RTL and gate level netlist.
• Review industry standard specifications and augment test plan to improve verification quality.
• Participate in post silicon bring up, validation and compliance testing and debug.
• Collaborate with cross-functional teams and present in design reviews.

Skills

UVM

SystemVerilog

ASIC verification

communication

Education

Bachelor’s in Electrical Engineering

Tools

Git

Jira

Jenkins

Job description

Responsibilities

• Performs and supervises detailed Simulation, verification and validation of integrated circuits.
• Develop testbenches using System Verilog and UVM for functional and power aware RTL.
• Develop UVM components such as agents (active and passive), scoreboards, environment, assertions, and functional coverage.
• Develop test plan, UVM based test sequences, layered sequences, and virtual sequencers.
• Drive closure of verification metrics to cover verification space; work with the team to identify and close gaps in functional, power aware and gate level timing simulation.
• Provide regression setup and debug of RTL and gate level netlist.
• Review industry standard specifications and augment test plan to improve quality of verification.
• Participate in post silicon bring up, validation and compliance testing and debug.
• Work collaboratively with cross‑functional teams such as product architect, designers, project leads, and project managers.
• Serve as subject matter expert in customer communications, including presentations in design reviews, representation on weekly conference calls, and ensuring schedule adherence.

Qualifications

• Bachelor’s in electrical engineering or equivalent and 12+ years of experience.
• Proven expertise with UVM and/or System Verilog based verification.
• Excellent understanding of ASIC verification methodologies and proven experience in verification.
• Experience working with source control tools, bug management tools and release management tools such as Jenkins, Git, and Jira.
• Strong written and verbal communication skills and ability to work independently.

We embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we are committed to give all applicants and employees equal opportunities.