ASIC DFT Engineering Technical Leader | MBIST, SCAN, ATPG

Cisco Systems, Inc; Bengaluru Urban; On-site; INR 3,500,000 - 8,000,000; Full time

Job summary

Cisco Systems, Inc is seeking an ASIC Implementation Technical Lead in Bangalore, India, focusing on Design-for-Test (DFT) to support ATE, in-system test and post-silicon validation. You will lead DFT integration with RTL and collaborate across RTL, PD, and verification teams.

The role demands deep knowledge of JTAG, boundary scan, ATPG, and EDA tools, with extensive hands-on experience and strong problem-solving skills in a multifaceted environment. A Master’s degree is preferred.

Qualifications

• Bachelor's or a Master’s Degree in Electrical or Computer Engineering required with at least 10 years of experience.
• Knowledge of the latest innovative trends in DFT, test and silicon engineering.
• Experience with JTAG protocols, Scan and BIST architectures, including memory BIST and boundary scan.
• Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime
• Verification skills include System Verilog Logic Equivalency checking and validating the Test-timing of the design.
• Experience with JTAG protocols, Scan and BIST architectures, including memory BIST and boundary scan.
• Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime
• Experience working with Gate level simulation, debugging with VCS and other simulators.
• Post-silicon validation and debug experience; Ability to work with ATE patterns, P1687
• Strong verbal skills and ability to thrive in a multifaceted environment

Responsibilities

• Implement Hardware Design-for-Test (DFT) features supporting ATE, in-system test, debug and diagnostics.
• Develop innovative DFT IP in collaboration with multi-functional teams and integrate testability features in RTL.
• Work with design/verification and PD teams to enable integration and validation of test logic across implementation and post-silicon validation.
• Contribute to creating Innovative Hardware DFT and physical design aspects for new silicon device models and test/debug strategies.
• Craft solutions and debug with minimal mentorship across the implementation flow.

Skills

DFT design

JTAG/boundary scan

ATPG

Verilog

Test automation

VCS debugging

Test timing validation

Communication skills

Education

Bachelor's or Master’s in Electrical/Computer Engineering

Tools

TestMax

Tetramax

Tessent

PrimeTime

VCS

Job description

The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. With ~2,100 employees across 16 countries, we design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry.

You will be in the Silicon One development organization as an ASIC Implementation Technical Lead in Bangalore India with a primary focus on Design-for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. As a member of this team you will also be involved in crafting groundbreaking next generation networking chips. You will help lead to drive the DFT and quality process through the entire Implementation flow and post silicon validation phases with additional exposure to physical design signoff activities.

Your Impact

• Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs.
• Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL.
• Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows.
• Your team will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies.
• The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship.

Minimum Qualifications:

• Bachelor's or a Master’s Degree in Electrical or Computer Engineering required with at least 10 years of experience.
• Knowledge of the latest innovative trends in DFT, test and silicon engineering.
• Experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan.
• Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime
• Verification skills include, System Verilog Logic Equivalency checking and validating the Test-timing of the design
• Experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan.
• Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime
• Experience working with Gate level simulation, debugging with VCS and other simulators.
• Post-silicon validation and debug experience; Ability to work with ATE patterns, P1687
• Strong verbal skills and ability to thrive in a multifaceted environment

Preferred Qualifications:

• Verilog design experience - developing custom DFT logic & IP integration; familiarity with functional verification
• DFT CAD development - Test Architecture, Methodology and Infrastructure
• Test Static Timing Analysis