Principal Cache RTL Design - CPU Team

Advanced Micro Devices, Inc.; Bengaluru; Hybrid; INR 3,000,000 - 6,000,000; Full time

Job summary

Advanced Micro Devices, Inc. (AMD) is seeking a PMTS Silicon Design Engineer to drive RTL design of high-performance x86-core features and power management across IPs. You will collaborate across teams to optimize designs, address inter-IP integration, and mentor junior RTL engineers.

You will lead architecture decisions, linting, and verification efforts, while engaging with DFT, Physical Design, and SOC groups to deliver robust silicon blocks.

Qualifications

• 15+ years of experience in Digital IP/ASIC design and Verilog RTL development.

Responsibilities

• RTL design of high performance x86-core ISA features, clock/reset/power features of processor, IP integration, sub-system level design.
• Architect and design of power management features, cache, coherency.
• Design optimization for power-efficient IP using low power techniques.
• Coordinate inter IP integration and resolve issues.
• Own Clock-Domain crossing and linting aspects of RTL and subsystem.
• Work with DFT, Physical Design and SOC teams to implement feedback.
• Architect, document, and lead RTL design features.
• Mentor juniors and drive tasks to completion.
• Represent AMD to external technical communities and vendors.

Skills

RTL design

Power management

Cache coherency

Clock-Domain Crossing

DFT

Physical Design

SOC

Verilog RTL

Digital IP/ASIC

Scripting (Python/Perl)

Leadership

Communication

Design verification

Education

Master's degree in Electrical/Electronics Engineering, Computer Engineering, or VLSI design Engineering

Tools

Verilog RTL

Front-end EDA tools

EDA workflows

Job description

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

PMTS SILICON DESIGN ENGINEER

THE PERSON:

You have a passion for modern, complex processor architecture, digital design as well as verification/design quality. You are a team player who has excellent communication skills, strong analytical & problem-solving skills and are willing to learn and ready to take on problems. A global mindset and ability to work in a multi – site environment are keys to being successful in this role.

KEY RESPONSIBILITIES:

• RTL design of high performance x86-core ISA features, clock/reset/power features of processor, IP Integration, sub-system level design
• Architect and design of power management features, cache, coherency.
• Design optimization for implementing power efficient IP, implementing the RTL using low power techniques
• Responsible for the inter IP integration issues resolution
• Own the Clock-Domain crossing, Linting aspects of the overall design of the IP and the subsystem.
• Work closely with DFT, Physical Design and SOC teams to incorporate the interdisciplinary feedback into the design
• Architecting, micro-architecting and documentation of the design features
• Lead design team from all aspects of the RTL deliverables.
• Mentor the junior members of the RTL team to meet the team goals
• Represents AMD to the outside technical community, partners and vendors
• Your commitment to innovating as a team demonstrated through excellent communication, knowledge of proper documentation techniques, and independently driving tasks to completion.

PREFERRED EXPERIENCE:

• 15+ years of experience in Digital IP/ASIC design and Verilog RTL development
• Experience in full IP design cycle, requirements definition, architecture and microarchitecture specification.
• Should be well versed with RTL design verification, design quality checks, synthesis, timing closure and post silicon validation.
• Expert on Verilog RTL design and has experience of multiscale digital IP/ASIC projects.
• Should possess expertise in front-end EDA tools sign-off and its flows.
• Familiarity with low power design and low power flow is an added plus.
• Ability to program with scripting languages such as Python or Perl is a plus;
• Highly motivated to seek out solutions and willing to learn new skills to fulfill job requirements;
• Proven interpersonal skills, leadership and teamwork;
• Excellent writing skills in the English language, editing and organizational skills required;
• Skilled at prioritization and multi-tasking;
• Good understanding of engineering terminology used within the semiconductor industry;
• Good understanding of digital design concepts;
• Knowledge of, or experience in, functional design verification or design is highly desired.

ACADEMIC CREDENTIALS:

Master’s degree preferred with emphasis in Electrical/Electronics Engineering, Computer Engineering, or VLSI design Engineering.

#LI-RR1

#LI-Hybrid

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.