Sr IP/CPU RTL Design Lead - CPU Team

AMD; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Benefits offered by this job

AMD benefits

Job summary

AMD in Bengaluru (India) is seeking an experienced SMTS Silicon Design Engineer to lead RTL design for high‑performance x86 core features. You will architect power management and cache systems, drive IP integration, and ensure robust RTL quality across cross-functional teams.

The role emphasizes leadership, mentoring, and collaboration with DFT, PHY, and SOC groups. You should bring 12+ years in Digital IP/ASIC design, strong Verilog RTL expertise, and a track record of delivering complex RTL

Qualifications

• 12+ years of experience in Digital IP/ASIC design and Verilog RTL development.
• Experience in full IP design cycle, requirements, architecture and microarchitecture.
• Expertise in RTL design verification, synthesis, timing closure and post-silicon validation.
• Proficiency in Verilog RTL and multiscale digital IP/ASIC projects.
• Familiarity with sign-off and flows of front-end EDA tools.
• Knowledge of low power design and RTL power techniques is a plus.
• Strong problem solving, communication and leadership abilities.

Responsibilities

• RTL design of high performance x86-core features and IP integration.
• Architect and design power management features and cache coherency.
• Optimize designs for power efficiency and implement RTL with low power techniques.
• Resolve inter-IP integration issues and own clock-domain crossing tasks.
• Collaborate with DFT, physical design and SOC teams for feedback.
• Architect and document design features; lead RTL deliverables.
• Mentor junior RTL team members and drive tasks to completion.
• Represent AMD to external technical communities and vendors.

Skills

Verilog RTL design

Digital IP/ASIC design

RTL verification

Synthesis & timing closure

Leadership & mentoring

Python/Perl scripting

Education

Master’s degree in EEE/EC/VDES/VLSI

Tools

Front-end EDA tools

Job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

SMTS SILICON DESIGN ENGINEER

THE PERSON:

• You have a passion for modern, complex processor architecture, digital design as well as verification/design quality. You are a team player who has excellent communication skills, strong analytical & problem-solving skills and are willing to learn and ready to take on problems. A global mindset and ability to work in a multi – site environment are keys to being successful in this role.

KEY RESPONSIBILITIES:

• RTL design of high performance x86-core ISA features, clock/reset/power features of processor, IP Integration, sub-system level design
• Architect and design of power management features, cache, coherency.
• Design optimization for implementing power efficient IP, implementing the RTL using low power techniques
• Responsible for the inter IP integration issues resolution
• Own the Clock-Domain crossing, Linting aspects of the overall design of the IP and the subsystem.
• Work closely with DFT, Physical Design and SOC teams to incorporate the interdisciplinary feedback into the design
• Architecting, micro-architecting and documentation of the design features
• Lead design team from all aspects of the RTL deliverables.
• Mentor the junior members of the RTL team to meet the team goals
• Represents AMD to the outside technical community, partners and vendors
• Your commitment to innovating as a team demonstrated through excellent communication, knowledge of proper documentation techniques, and independently driving tasks to completion.

Preferred Experience

• 12+ years of experience in Digital IP/ASIC design and Verilog RTL development
• Experience in full IP design cycle, requirements definition, architecture and microarchitecture specification.
• Should be well versed with RTL design verification, design quality checks, synthesis, timing closure and post silicon validation.
• Expert on Verilog RTL design and has experience of multiscale digital IP/ASIC projects.
• Should possess expertise in front-end EDA tools sign-off and its flows.
• Familiarity with low power design and low power flow is an added plus.
• Ability to program with scripting languages such as Python or Perl is a plus;
• Highly motivated to seek out solutions and willing to learn new skills to fulfill job requirements;
• Proven interpersonal skills, leadership and teamwork;
• Excellent writing skills in the English language, editing and organizational skills required;
• Skilled at prioritization and multi-tasking;
• Good understanding of engineering terminology used within the semiconductor industry;
• Good understanding of digital design concepts;
• Knowledge of, or experience in, functional design verification or design is highly desired.

Academic Credentials

Master’s degree preferred with emphasis in Electrical/Electronics Engineering, Computer Engineering, or VLSI design Engineering.

Benefits offered are described: AMD benefits at a glance.

AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.