ASIC Engineering Technical Leader (RTL Design | 8- 15 Years | Bangalore)

Cisco Systems, Inc; Bengaluru; On-site; INR 3,500,000 - 6,000,000; Full time

Job summary

Cisco Systems, Inc. SiliconOne team in Bengaluru is seeking an expert ASIC Engineering Technical Leader with hands-on RTL design and a deep background in ASIC/SoC development—from specification through tape-out and lab validation.

You will drive architectural decisions and guide complex implementations. You will document and improve standard methodologies, lead a cross-functional team, and ensure high-performance, low-power designs for scale.

Qualifications

• BS/MS with 8+ years hands-on experience in large-scale ASIC design.
• Experience in system debug and SW/HW bringup and silicon validation.
• Gate-level RTL and synthesis understanding.
• Strong written and verbal communication and leadership.
• Experience in architecture of high-performance ASICs and flow automation.

Responsibilities

• Architectural work with deep understanding of architecture and problem solving.
• All aspects of implementation: specification, timing, power optimization, flow automation.
• Document and improve standard methodologies to ensure product success.

Skills

RTL design

ASIC/SoC development

System debug

Leadership

Interpersonal skills

Education

BS in Electrical/Computer Engineering

MS in Electrical/Computer Engineering

Tools

Scripting

Makefiles

Synthesis tools

Job description

Come join us and be part of the Cisco SiliconOne team and take part in crafting Cisco's groundbreaking Enterprise and Service Provider solutions by crafting some of the most complex chips being developed in the industry with the opportunity to get full exposure to all aspects of the systems and applications we build (Silicon, Hardware, Software, telemetry, security, etc). Our group offers a rare combination of a startup culture with the benefits of working for the top tier networking company in the world!

Your Impact

Cisco SiliconOne team is looking for an expert and talented ASIC Engineering Technical Leader. You will have an ASIC design background with hands-on experience in RTL design with in-depth knowledge of ASIC/SoC development cycle, the best industry practices, from specification through tape-out and lab validation, and a proven track record of success in high-performance/high-volume products.

• Architectural work: in-depth understanding of the architecture, and identification of problems and solutions.
• All aspects of implementation: specification, design, timing-analysis, power-optimization, flow automation, optimization of the logic for low power and area; highlighting issues and standard methodologies for power and area optimization.
• Document and improve standard methodologies to make product successful.

Minimum Qualifications

• BS/MS and 10+/8+ years respectively of hands-on experience in large-scale, high-performance ASIC
• Experienced in system debug and SW/HW bringup, system validation of silicon towards FCS.
• Gate-level understanding of RTL and Synthesis
• Good written/verbal interpersonal skills and leadership skills.

Preferred Qualifications

• Worked in architecture and definition of high-scale, high-performance ASICs.
• Validated experience in implementation: specification, RTL design, lint, cdc, timing analysis, formal verification, system testing.
• Validated experience in flow automation (scripting, Makefiles, etc), and establishing guidelines for the team.
• Good interpersonal skills, and validated leadership to accurately describe issues/improvements and lead team for on-time completion.