Sr. Engineer, Silicon Validation

Ayar Labs; Bengaluru; On-site; INR 1,800,000 - 3,000,000; Full time

Job summary

Ayar Labs in Bengaluru, on-site with flexible hours, seeks a Senior Engineer to lead silicon validation of optical chiplets. You will define validation strategy from pre-silicon to post-silicon signoff, collaborating with firmware and design teams to ensure core functionality at tape-out.

This role emphasizes SerDes, photonic systems, and rigorous test methodologies. Ideal candidates have 5–8 years in validation, strong Python automation, and deep knowledge of Ethernet/PCIe.

Qualifications

• Bachelor degree in Electrical Engineering or related field with 5-8 years of relevant experience.
• Masters degree with 5-8 years of experience.
• Leadership in pre-silicon and post-silicon validation for complex SoCs.
• Hands-on high-speed SerDes validation using BERTs, oscilloscopes, and network analyzers.
• Strong Python for lab automation, data analysis, and test infrastructure.
• End-to-end validation test plan ownership.
• Deep understanding of Ethernet/PCIe and related protocols.
• Excellent cross-functional communication.

Responsibilities

• Define and implement validation methodologies for electronic-photonic SoCs.
• Lead first silicon bring-up and power-on with firmware and design teams.
• Perform post-silicon validation of SerDes interfaces and optical control loops.
• Apply IEEE, OIF, JEDEC standards and establish signoff criteria.
• Investigate silicon failures and drive to closure with design/firmware.
• Mentor senior and junior validation engineers on best practices.
• Produce validation reports and signoff packages.

Skills

Leadership

Pre-silicon validation

Post-silicon validation

First silicon bring-up

Sign-off processes

High-speed SerDes validation

Python for lab automation

Test plan ownership

Cross-functional collaboration

Communication skills

Mentoring

Education

Bachelor's degree in Electrical Engineering

MSEE or equivalent

Tools

BERTs

Oscilloscopes

DCA

Network analyzers

OSA

VNA

Job description

Location: Bengaluru, India

Job Id:608

# of Openings:0

Senior Engineer, Silicon Validation

Location: Bengaluru (on-site, hours flexible)

Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models.

Backed by industry giants like NVIDIA, AMD, MediaTek and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to unleashing next-generation AI scale-up architectures.

In this role, you will lead the silicon validation of our optical chiplets. You will define and drive the validation strategy from pre-silicon validation and preparation with emulation/FPGA platforms, tape out qualification, initial silicon power-on through block and chip level signoff. This is a rare opportunity to apply deep expertise in high-speed SerDes, photonic systems, pre-silicon and post-silicon validation to shape the future of optical interconnect for next-generation AI infrastructure.

Essential Functions

• Lead Validation Strategy: Define and implement comprehensive validation methodologies for our electronic-photonic SoCs, covering pre-silicon validation, initial bringup, functional validation, electrical characterization, and system-level testing. Develop detailed test plans, success criteria, and select appropriate test equipment and methodologies.
• Drive Silicon Bring-up: Lead first silicon power-on and bringup for new tape-outs, collaborating with firmware and design teams to establish operating conditions and validate core functionality from day one.
• Own Block and System Validation: Execute rigorous post-silicon validation of SerDes interfaces, optical control loops, and mixed-signal blocks using industry-standard lab equipment (BERT, DCA, oscilloscopes, OSA, VNA).
• Apply Standards and Best Practices: Draw on industry standards (IEEE, OIF, JEDEC, Ethernet/Optical MSA specs) and semiconductor validation best practices to establish rigorous validation targets, coverage objectives, and signoff criteria.
• Root Cause and Debug: Investigate and drive to closure all silicon failure modes, from signal integrity issues to mixed-signal anomalies, using systematic debug methodologies and close collaboration with design and firmware teams.
• Mentor and Lead: Provide technical leadership and mentorship to senior and junior validation engineers; guide the team's technical execution.
• Deliver High Quality Documentation: Create and maintain comprehensive validation reports, signoff packages, and product performance documentation.

Required Qualifications

• Bachelor degree in Electrical Engineering or related field with 5-8 years of relevant industry experience, or Masters degree with 5-8 years of experience.
• Demonstrated leadership in pre-silicon, post-silicon validation for complex SoCs or multi-chip packages, including first silicon bringup and full signoff.
• Hands-on expertise with high-speed SerDes validation and characterization (NRZ and PAM-4) using equipment such as BERTs, oscilloscopes/DCAs, and network analyzers.
• Strong proficiency in Python for lab automation, data analysis, and test infrastructure development.
• Experience developing and owning validation test plans end-to-end.
• Deep understanding of communication protocols and standards (Ethernet, PCIe, etc).
• Excellent communication skills and ability to drive cross-functional technical alignment.

Preferred Qualifications

• MSEE or equivalent
• Familiarity with optical transceiver standards and co-packaged optics integration challenges.
• Knowledge of high-speed standards: Ethernet (200G/400G/800G), PCIe Gen5/6, OIF CEI.
• Experience driving NPI and transition from lab validation to manufacturing test.