Omni Design Technologies is a leading provider of high-performance, ultra-low power IP cores, from 28nm down through advanced FinFET nodes, which enable differentiated SoC in applications ranging from 5G, wireline, optical communications, LiDAR, radar, automotive networking, AI, image sensors, and the IoT.
Our data converter (ADC and DAC) IP cores range from 6-bit to 14-bit resolution and from a few MSPS to more than 100 GSPS sampling rates. Omni Design, founded in 2015 by semiconductor industry veterans, has an excellent track record of innovation and collaboration with customers to enable their success. The company is headquartered in Milpitas, California with additional design centers in Fort Collins-Colorado, Bangalore-India, Hyderabad-India, Dublin-Ireland, Boston-Massachusetts.
Physical Design Manager
Full-time / Hybrid
Omni Design is developing exciting high-speed Mixed‑Signal SOC. We are looking for a Lead/Manager of Physical Design to make these high‑performance Mixed‑Signal SOCs a reality.
Role and Responsibility
- Own and drive the physical implementation of next-generation Mixed‑Signal SOC with HS ADC/DAC, HS interfaces like PCIe, LPDDR, MIPI, USB2/3, Gig Ethernet etc.
- Understand the requirements and define physical implementation methodologies.
- Collaborate with architecture, design, front‑end and CAD teams to deliver high‑quality physical designs.
- Implement and verify designs at all levels of hierarchy in the SOC.
- Interact with foundry over matters of technology, schedule, and sign‑off.
Qualifications and Experience
- BSEE Required, MSEE Preferred.
- 10+ years of experience in physical design in SOCs.
- 3+ years of experience in managing projects and leading teams.
- Hands‑on expertise in Floorplanning, Power planning, Implementation of UPF Methodology, Logic and clock tree synthesis, Placement, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR.
- Full chip/top‑level expertise in multiple chip tape‑outs.
- Good understanding and experience in SCAN, BIST, and ATPG.
- Strong background in TCL/Perl/Python programming is a must.
- Expertise in double patterning process nodes and experience with sub‑40 nm nodes required.
- Expertise in Cadence or Synopsys RTL‑to‑GDSII flow is preferred.
- Do the FC Floor Plan and Layout; Set up the EDA tools and develop the scripts; Develop the UPF methodology; Implement the Power, Clock Grid; Generate the SDF files.
- Do the DRC, ERC, LVS, SI and Crosstalk checks, Do the DFM checks; Tapeout the chip; Manage and mentor the PD and custom layout team; Make changes as needed to the custom layout of the IP; Release the GDS2 to the fabs.
Contact
"Mining The Knowledge Community"
Seniority level
Mid‑Senior level
Employment type
Full‑time
Job function
Design, Research, and Engineering
Industries: Semiconductor Manufacturing, Computer Hardware Manufacturing, and Software Development