Physical Design Engineers - 2 openings

Kandou Bus SA; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

Kandou is redefining AI hardware economics with a MIMO-over-copper architecture and a scalable, energy-efficient chiplet-based AI memory fabric. We are actively seeking Physical Design Engineers based in Hyderabad OR Bangalore.

Join Kandou to drive first-time-right silicon production, timing closure, and advanced PD flows in a fast-growing semiconductor company. 10+ years in the field and strong Cadence experience are required.

Qualifications

• 10+ years’ experience in the semiconductor industry, with min. 5 years in a digital Physical Design technical leadership role
• Experience on modern semiconductor process technologies including 28nm, 14/16nm, 7nm
• Experienced user of EDA tools for design and verification such as, Cadence Genus and Innovus, LEC, Calibre/PVS DRC/LVS, parasitics extraction, EM and IR drop, ESD, etc.
• Expertise in Timing Constraints and Static Timing Analysis (STA)
• Experience in CPF/UPF technologies and flows is highly desirable
• Exposure to flip-chip package technologies and wire bond package technologies
• Experience in hierarchical floor planning and implementation
• Experience in release management and tape out procedures
• Experience in library setup and flow development with focus on cross project reusability
• Experience in DFT methodologies and implementation schemes

Responsibilities

• As a Physical Design Engineer, you will work closely with the Architecture, RTL, DFT teams to ensure first-time-right high-volume silicon production
• Timing constraints improvement and timing constraints validation, signoff Static Timing Analysis and block-level timing closure
• Synthesis, block level floor-planning, power grid design, place & route, clock tree synthesis, electromigration / IR-Drop analysis, power/signal integrity analysis, crosstalk analysis, formal equivalence checking and physical verification (DRC / LVS / Antenna)
• Participate in developing improvements to scripts/methodologies/flows
• Interact closely with the design team to understand requirements and implement solutions as also helping on providing design views for use with digital PD flows (LIB, LEF, DEF, GDS, SPEF, etc.)
• Support IP and chip level integration
• Support and interact with customers on requirements and IP delivery
• Manage workload and schedule and report to internal management team

Skills

RTL to GDS flow

Scripting: Python/TCL

Team player

Documentation

Education

Bachelors/Masters in Electronics and Electrical Engineering or Computer Science

Tools

Cadence Genus

Cadence Innovus

Calibre / DRC LVS

Parasitics extraction

Job description

At Kandou, we are redefining the economics of AI infrastructure. Our mission is to democratise AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems — a critical barrier to scalable adoption.

Our proprietary MIMO-over-copper technology powers a high-performance, chiplet-based AI memory fabric that is both scalable and energy-efficient. Unlike traditional interconnects, our solution reduces power consumption significantly while preserving high bandwidth and ultra-low latency — unlocking unprecedented efficiency for AI training and inference at scale.

Kandou’s architecture is not just an incremental improvement — it’s a foundational shift in how AI

hardware is built for the future.

We are actively seeking Physical Design Engineers based in Hyderabad OR Bangalore

Required competences - Experience

• 10+ years’ experience in the semiconductor industry, with min. 5 years in a digital Physical Design technical leadership role

• Experience on modern semiconductor process technologies including 28nm, 14/16nm, 7nm

• Experienced user of EDA tools for design and verification such as, Cadence Genus and Innovus, LEC, Calibre/PVS DRC/LVS, parasitics extraction, EM and IR drop, ESD, etc.

• Expertise in Timing Constraints and Static Timing Analysis (STA)

• Experience in CPF/UPF technologies and flows is highly desirable

• Exposure to flip-chip package technologies and wire bond package technologies

• Experience in hierarchical floor planning and implementation

• Experience in release management and tape out procedures

• Experience in library setup and flow development with focus on cross project reusability

• Experience in DFT methodologies and implementation schemesRequired

Competencies – Skills

Required competences - Skills

• Good understanding of RTL to GDS implementation flow (synthesis, P&R, LEC, PV)

• Self-motivated, with strong sense of ownership and responsibility. Good communicator and team player

• Good scripting capabilities (shell, TCL, Python, make) and good understanding of data management (revision control system)

Responsibility and Authority

Responsibility and Authority

• As a Physical Design Engineer, you will work closely with the Architecture, RTL, DFT teams to ensure first-time-right high-volume silicon production

• Timing constraints improvement and timing constraints validation, signoff Static Timing Analysis and block-level timing closure

• Synthesis, block level floor-planning, power grid design, place & route, clock tree synthesis, electromigration / IR-Drop analysis, power/signal integrity analysis, crosstalk analysis, formal equivalence checking and physical verification (DRC / LVS / Antenna)

• Participate in developing improvements to scripts/methodologies/flows

• Interact closely with the design team to understand requirements and implement solutions as also helping on providing design views for use with digital PD flows (LIB, LEF, DEF, GDS, SPEF, etc.)

• Support IP and chip level integration

• Support and interact with customers on requirements and IP delivery

• Manage workload and schedule and report to internal management team

Education

• Bachelors/Masters of Engineering in Electronics and Electrical Engineering/Computer Science (equivalent or higher)

https://www.kandou.ai/