Physical Design - Engineer

QUALCOMM, Inc.; Chennai; On-site; INR 900,000 - 1,300,000; Full time

Job summary

Qualcomm India Private Limited invites experienced engineers for Physical Implementation within the Engineering Group. The role covers Floor-planning, Place and Route, CTS, DRC/LVS, PDN, and Timing Closure across high-frequency cores.

The ideal candidate has hands-on PnR experience using ICC2 and Innovus, strong scripting (Tcl/Perl), and a collaborative mindset to align design, DFT and PNR teams while optimizing power and performance. 3-6 years required.

Qualifications

• Bachelor's degree required in CS/EE or related field.
• 3-6 years experience in physical implementation and PnR.
• Experience with PD, PPA trade-offs, timing convergence, and STA.

Responsibilities

• Physical Implementation activities including floor-planning, Place and Route, CTS, DRC/LVS, PDN, and Timing Closure and power optimization.
• Contribute to PD implementation for PPA-critical cores and make PPA trade-offs.
• Collaborate with design, DFT and PNR teams to resolve constraints and verify STA and physical design.
• Knowledge of clocking architecture and high-frequency data-path timing convergence.

Skills

Problem solving

Communication skills

Education

Bachelor's degree in CS / EEE / related field

Tools

Tcl scripting

Perl scripting

Synopsys ICC2

Cadence Innovus

PTSI/Tempus

Job description

Company:

Qualcomm India Private Limited

Job Area:

Engineering Group, Engineering Group > Hardware Engineering

General Summary:

• Physical Implementation activities for Sub systems which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization.
• Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions.
• Knowledge in timing convergence of high frequency data-path intensive Cores and advanced STA concepts
• Well versed with the Block level PnR convergence with Synopsys ICC2 / Cadence Innovus and timing convergence in PTSI / Tempus in latest technology nodes
• Good understanding of clocking architecture.
• Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc.
• Well versed with Tcl/Perl Scripting
• Strong problem-solving skills and good communication skills.

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

3-6 yrs Experience required.

Applicants: Qualcomm is an equal opportunity employer.

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