PDK Engineer Extraction Development

Intel; Bengaluru; Hybrid; INR 3,500,000 - 7,000,000; Full time

Job summary

Intel in Bengaluru seeks an experienced PDK Engineer to develop and validate PDK collateral, ensuring quality for advanced silicon designs. You will maintain design environments, run parasitic extraction, and collaborate with EDA vendors to optimize design flows.

The role emphasizes automation, scalability, and cross‑functional teamwork across design and manufacturing to advance Intel's process technologies and enable robust design methodologies.

Qualifications

• Bachelor's degree in Electrical/Computer Engineering or related field with 12+ years of PDK development experience.
• Hands-on experience with Calibre, Pegasus or ICV for physical verification.
• Experience with parasitic extraction tools such as StarRC or QRC.
• Proficient in Python, TCL or PERL for automation.

Responsibilities

• Develop and maintain PDK collateral and runsets for silicon designers.
• Validate PDK libraries for design rules and advanced nodes.
• Build test structures and simulate PV, parasitic extraction, and device modeling.
• Collaborate to resolve PDK issues and perform root-cause analysis.
• Drive automation by creating QA methodologies and tools.
• Partner with EDA vendors to enable new tools and improve workflows.
• Document design flows, guidelines, and tutorials.
• Engage cross-functional teams to support process development.

Skills

Python scripting

TCL scripting

PERL scripting

Physical verification

Parasitic extraction

PDK enablement

Education

Electrical/Computer Engineering degree

Tools

Calibre

Pegasus

ICV

StarRC

QRC

Job description

The Role And Impact

As a Process Design Kit (PDK) Engineer, you will play a pivotal role in developing and ensuring the quality of PDK collateral that enables cutting‑edge silicon designs. You will be responsible for maintaining and validating design environments for specific technology nodes, working on parasitic extraction, physical verification, and design methodologies to set the foundation for high‑quality, efficient design flows. This role is integral to advancing Intel's product lines and ensuring seamless collaboration across design and manufacturing teams.

Business Group

You will join the Design Technology Platform Enablement group, which focuses on creating world‑class design environments to support Intel's advanced process technologies. This group collaborates with design teams, EDA vendors, and technology development experts to deliver high‑quality design tools and methodologies that drive innovation across Intel's product offerings.

Key Responsibilities

• Develop and maintain PDK collateral, including Metal R and C extraction, runsets, LVS , physical design verification decks, and modeling transistors for silicon designers.
• Perform validation for PDK libraries, ensuring compliance with design rules and correct implementations for advanced process nodes.
• Build test structures and simulate physical verification, parasitic extraction, and device modeling to deliver high‑quality design solutions.
• Collaborate with stakeholders to resolve PDK‑related issues, including debugging, root cause analysis, and error dispositioning.
• Drive automation and scalability by developing QA methodologies and tools to enhance coverage across technology nodes.
• Partner with EDA vendors to enable new tool functionalities and improve design workflows.
• Document and deliver design flows, guidelines, and tutorials to optimize usability for internal and external design communities.
• Engage with cross‑functional teams to support new process development and ensure ease of use for the design ecosystem.

Qualifications

Minimum Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, with 12+ years of experience; OR Master's degree with 10+ years of experience; OR Ph.D. with 8+ years of experience in PDK development and validation.
• Hands‑on expertise in physical verification tools such as Calibre, Pegasus, or ICV, and parasitic extraction tools such as StarRC or QRC.
• Proficiency in scripting languages such as Python, TCL, or PERL for automation and workflow optimization.
• Demonstrated experience with PDK enablement for advanced process nodes, including device modeling and layout verification methodologies.

Preferred Qualifications

• Familiarity with reliability verification techniques, including EM/IR flows and ESD concepts.
• Knowledge of CMOS device physics, process technology, and design rules.
• Experience with 3DIC flow methodologies and low‑power techniques.
• Strong organizational, presentation, and communication skills to collaborate effectively with cross‑functional teams and vendors.

We're looking for innovative, detail‑oriented individuals who thrive in dynamic environments and are eager to make a meaningful impact on Intel's design technology platform. Join us and be part of a team that drives technological excellence and shapes the future of semiconductor innovation.

Job Type

Experienced Hire

Shift

Shift 1 (India)

Primary Location

India, Bangalore

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on‑site at their assigned Intel site and off‑site. Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION

Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.