PDK Engineer

Intel; Bengaluru; On-site; INR 1,800,000 - 2,800,000; Full time

Job summary

Intel in Bangalore, India, is seeking a DRC Runset Engineer to develop, validate, and optimize design rule checks for advanced semiconductor nodes. You will translate design rules into robust rule decks and work with process, design-rule owners, CAD/EDA teams to deliver production-quality checks.

The role requires hands-on experience with Calibre, ICV, Pegasus, Python or Perl scripting, and strong debugging and automation skills to improve runset quality, performance, and reliability in a

Qualifications

• Experience developing DRC runsets and rule decks for semiconductor tech nodes.
• Hands-on with Calibre, ICV, Pegasus and related physical verification tools.
• Strong debugging, automation, and problem-solving skills.
• Good understanding of layout rules and verification concepts.

Responsibilities

• Develop, maintain, and support DRC runsets/rule decks for advanced nodes.
• Translate process design rules into accurate physical verification checks.
• Create test cases to validate rule deck functionality and coverage.
• Debug runset issues and resolve customer/user-reported problems.
• Automate rule deck development, validation, regression, and deployment.
• Collaborate with process developers, CAD teams, and design groups.

Skills

Python

Perl

Tcl

Shell scripting

Education

Bachelor's in Electronics / VLSI / CE

Master's in Electronics / VLSI / CE

Tools

Calibre

ICV

Pegasus

Cadence Virtuoso

Calibre DRV

IC WorkBench

Job description

Job Details:

Job Description: We are looking for a skilled DRC Runset Engineer to develop, validate, support, and optimize Design Rule Checking runsets for advanced semiconductor process technology nodes. The candidate will work closely with process development teams, design rule owners, CAD/EDA teams, and design groups to translate design rules into robust, efficient, and production-quality rule decks. The role requires strong expertise in DRC rule deck development using industry-standard physical verification tools such as Siemens Calibre, Synopsys ICV, and Cadence Pegasus, along with strong debugging, automation, and problem-solving skills.

Key Responsibilities

• Develop, maintain, and support DRC runsets/rule decks for advanced semiconductor process nodes.
• Translate process design rules into accurate and efficient physical verification checks.
• Develop and validate complex geometric, connectivity, density, and process‑specific design rule checks using tools such as Calibre, ICV, and Pegasus.
• Create comprehensive test cases to validate rule deck functionality, coverage, and correctness.
• Debug DRC rule deck issues and resolve customer/user-reported problems.
• Improve runset quality, runtime efficiency, scalability, and usability.
• Work closely with process developers, design rule owners, CAD teams, and design teams to collect, understand, and refine requirements.
• Automate rule deck development, validation, regression, and deployment processes to improve efficiency and quality.
• Design and implement unit-level and end-to-end validation methodologies for DRC runsets and physical verification flows.
• Provide solutions for complex physical verification and design rule implementation challenges.
• Guide team members on technical issues, debugging strategies, and best practices.
• Use AI‑based tools and automation techniques to improve rule deck development, validation, and debug productivity.
• Support production users and resolve runset‑related issues in a timely manner.
• Work in a fast‑paced, dynamic environment with strong ownership, creativity, and attention to quality.

Qualifications

• 10+years of experienced Bachelor's or 8+ years of experienced Master's degree in Electronics, VLSI, Computer Engineering, or a related field.
• Strong experience in DRC rule deck/runset development for semiconductor technologies.
• Hands‑on expertise with one or more physical verification tools Siemens Calibre, Synopsys ICV, Cadence Pegasus
• Good understanding of semiconductor manufacturing process, layout design rules, and physical verification concepts.
• Experience in writing, debugging, and optimizing DRC checks.
• Hands‑on experience with layout and debug tools Cadence Virtuoso, Calibre DRV, IC WorkBench
• Strong programming/scripting skills in languages such as Python, Perl, Tcl, Shell scripting
• Ability to create and maintain validation test cases and regression suites.
• Strong debugging, analytical, and problem‑solving skills.
• Ability to work with cross‑functional teams and communicate effectively with technical stakeholders.
• Experience in automation of runset development, validation, and release processes.

Job Type: Experienced Hire

Shift: Shift 1 (India)

Primary Location: India, Bangalore

Additional Locations:

Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust N/A

Work Model for this Role: This role will require an on‑site presence. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.