NPU/AI Processor Synthesis Lead

Qualcomm; Bengaluru; On-site; INR 3,500,000 - 7,000,000; Full time

Job summary

Qualcomm seeks an NPU Synthesis Lead to drive RTL‑to‑gate synthesis for NPU IP and subsystems, while optimizing performance, power, and area across advanced silicon nodes.

You will collaborate with architecture, RTL, DFT, and physical design teams to ensure high‑quality netlists and QoR improvements, mentoring junior engineers and advancing synthesis flows and methodologies.

Qualifications

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
• Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
• PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Responsibilities

• Lead RTL‑to‑gate‑level synthesis for NPU IP and subsystems using industry‑standard tools (Synopsys Design Compiler, Cadence Genus).
• Develop and maintain synthesis scripts and flows for hierarchical and flat designs.
• Drive pre‑layout and post‑layout timing closure across multiple voltage and process corners.
• Collaborate with STA teams to resolve setup/hold violations.
• Apply physical‑aware synthesis techniques to meet aggressive PPA targets.
• Implement low‑power strategies using UPF/CPF flows.
• Validate and maintain SDC constraints for clocks, I/O delays, multi‑cycle paths, and false paths.
• Work closely with RTL design, DFT, and physical design teams for seamless handoff.
• Provide feedback to architecture and RTL teams for QoR improvements.
• Perform LEC, CLP, and linting.

Skills

Synthesis leadership

Timing closure

PPA optimization

RTL-to-gate synthesis

Cross-functional collaboration

Mentoring

Education

Bachelor's degree in CSE/EE or related

Master's degree in CSE/EE or related

PhD in related field

Tools

Synopsys Design Compiler

Cadence Genus

SDC constraints

UPF/CPF flows

Job description

The NPU Synthesis Lead will be responsible for driving synthesis and timing closure for Neural Processing Unit (NPU) IP and subsystems in cutting‑edge SoCs. This role involves leading synthesis flows, optimizing for PPA (Performance, Power, Area), and collaborating with architecture, RTL, and physical design teams to ensure high‑quality netlists for advanced technology nodes.

Key Responsibilities

• Synthesis Ownership
  • Lead RTL‑to‑gate‑level synthesis for NPU IP and subsystems using industry‑standard tools (Synopsys Design Compiler, Cadence Genus).
  • Develop and maintain synthesis scripts and flows for hierarchical and flat designs.
• Timing Closure
  • Drive pre‑layout and post‑layout timing closure across multiple voltage and process corners.
  • Collaborate with STA teams to resolve setup/hold violations.
• Power & Area Optimization
  • Apply physical‑aware synthesis techniques to meet aggressive PPA targets.
  • Implement low‑power strategies using UPF/CPF flows.
• Constraint Management
  • Validate and maintain SDC constraints for clocks, I/O delays, multi‑cycle paths, and false paths.
• Cross‑Functional Collaboration
  • Work closely with RTL design, DFT, and physical design teams for seamless handoff.
  • Provide feedback to architecture and RTL teams for QoR improvements.
• Quality Checks
  • Perform LEC (Logical Equivalence Check), CLP (Clock/Power checks), and linting.
• Flow Innovation
  • Explore advanced synthesis methodologies and EDA tool capabilities for better QoR.
• Team Leadership
  • Mentor junior engineers and drive best practices across synthesis and timing teams.

Minimum Qualifications

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
• Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
• PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Applicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e‑mail disability‑[e-mail] or call Qualcomm's toll‑free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities.