NoC Design Lead

Larsen & Toubro; Bengaluru; On-site; INR 4,500,000 - 7,500,000; Full time

Job summary

LTSCT — L&T Semiconductor Technologies Limited in Bangalore is hiring two NoC Design Leads to own the stacked Network-on-Chip that forms the data backbone of xPU — delivering 12 TB/s cross-section bandwidth. You will architect coherency, routing, QoS, and bandwidth allocation across BFOS arrays, SRAM banks, HBM controllers, UCIe links, and the host interface.

This role demands 10+ years of experience in on-chip interconnects, strong RTL/SystemVerilog expertise, and leadership to drive

Qualifications

• Ten-plus years designing on-chip interconnects/NoCs for high-performance SoCs.
• Deep understanding of NoC topologies, routing, QoS, and memory coherency.
• Expertise in RTL design (SystemVerilog) of routers, arbiters, buffers, CDC.

Responsibilities

• Architect and implement the 4-plane stacked NoC with high bandwidth targets.
• Define topology, routing, virtual channels, and arbitration to avoid deadlock.
• Design QoS and bandwidth allocation across BFOS arrays, SRAM banks, and HBM.
• Own on-chip coherency protocol and its interaction with HBM and host interface.
• Drive micro-architecture, RTL, and integration of routers, interfaces, and buffers.
• Model latency and congestion via cycle-accurate sim and traffic generators.
• Collaborate on floorplanning and verification coverage; drive QoR metrics.
• Mentor engineers and represent NoC in architecture/integration reviews.

Skills

NoC design

NoC topologies

MESI/MOESI coherency

SystemVerilog RTL

cycle-accurate simulation

performance modeling

HBM/UCIe familiarity

Python/Perl scripting

leadership

architecture/sys‑integration

Education

M.Tech/MS in EE/ECE/CS or equivalent

Tools

NoC generators/IP

Job description

(×2 openings) Location: Bangalore, India

Company: LTSCT — L&T Semiconductor Technologies Limited Reporting To: Chandra — Senior Architect, DC HW Systems

Experience: 10+ years (mandatory)

Role Summary

We are hiring two NoC Design Leads to own the stacked Network-on-Chip that forms the data backbone of xPU — 4 physical planes delivering 12 TB/s cross-section bandwidth. You will architect and implement coherency, routing, QoS, and bandwidth allocation across the BFOS arrays, banked SRAM, HBM controllers, UCIe links, and the host interface. This role is central to sustaining the extreme bandwidth and latency targets the compute architecture demands.

Key Responsibilities

• Architect and implement the 4-plane stacked NoC delivering 12 TB/s cross-section bandwidth across all on-chip and off-chip endpoints.
• Define topology, routing algorithms, virtual channels, and arbitration to guarantee deadlock-free, high-throughput data movement.
• Design QoS and bandwidth-allocation mechanisms balancing traffic between dual BFOS arrays, 512 SRAM banks, HBM controllers, UCIe, and host.
• Own the on-chip coherency protocol and its interaction with SRAM, HBM, and the host-interface coherency layer.
• Drive micro-architecture, RTL, and integration of routers, network interfaces, buffers, and clock-domain crossings.
• Model and analyze latency, bandwidth, and congestion via cycle-accurate simulation and traffic generators; close performance targets.
• Collaborate with PD on floorplan-aware NoC partitioning across the 4 physical planes and with DFT/verification on coverage.
• Define QoR/performance metrics, mentor engineers, and represent NoC in architecture and integration reviews.

Required Skills & Experience

• 10+ years designing on-chip interconnects/NoCs or coherent fabrics for high-performance SoCs.
• Deep understanding of NoC topologies (mesh, torus, crossbar, stacked/multi-plane), routing, flow control, and QoS.
• Strong grasp of cache-coherency protocols (MESI/MOESI-class, directory-based) and memory-consistency models.
• Expertise in RTL design (SystemVerilog) of routers, arbiters, buffers, and asynchronous/CDC interfaces.
• Hands-on performance modeling and analysis — cycle-accurate simulation, traffic modeling, bandwidth/latency closure.
• Experience with commercial or in-house NoC generators/IP and their integration methodology.
• Familiarity with high-bandwidth memory (HBM) and chiplet interconnect (UCIe) traffic characteristics.
• Proficiency in scripting (Python/Perl) for performance analysis and verification support.
• Strong micro-architecture, specification, and documentation skills.
• Demonstrated technical leadership and cross-team collaboration.

Preferred Qualifications

• Experience with multi-plane or 3D-stacked NoC architectures.
• Background in AI accelerator or GPU dataflow interconnects.
• Familiarity with formal verification of coherency/deadlock properties.
• M.Tech/MS in EE/ECE/CS or equivalent.