NoC Design Lead

Larsen & Toubro Limited; Bengaluru; On-site; INR 6,000,000 - 9,000,000; Full time

Job summary

L&T Semiconductor Technologies Limited invites two NoC Design Lead engineers to join Bangalore based DC HW Systems. You will own the stacked NoC delivering 12 TB/s bandwidth across on-chip and off-chip endpoints, and report to the Senior Architect.

You'll define topology, routing, QoS, and memory coherency, mentor engineers, and collaborate with PD/verification to meet latency targets; 10+ years experience required.

Qualifications

• 10+ years designing on‑chip interconnects/NoCs for high‑performance SoCs.
• Deep understanding of NoC topologies, routing, QoS.
• Strong cache‑coherency protocols knowledge.
• RTL design in SystemVerilog for routers and arbiters.
• Performance modeling and cycle‑accurate simulations.
• Familiarity with UCIe and HBM traffic.
• Scripting in Python/Perl for analysis.
• Strong documentation and cross‑team collaboration.

Responsibilities

• Architect and implement the 4-plane stacked NoC delivering 12 TB/s cross‑section bandwidth across all endpoints.
• Define topology, routing, virtual channels, and arbitration to guarantee deadlock‑free data movement.
• Design QoS and bandwidth‑allocation mechanisms balancing traffic between BFOS arrays, SRAM, HBM, UCIe, and host.
• Own the on‑chip coherency protocol and its interaction with SRAM, HBM, and host‑interface.
• Drive micro‑architecture, RTL, and integration of routers, network interfaces, buffers, and CDCs.
• Model latency, bandwidth, and congestion via cycle‑accurate simulation and traffic generators.
• Collaborate with PD on floorplan‑aware NoC partitioning and with DFT/verification on coverage.
• Define QoR/performance metrics, mentor engineers, and represent NoC in reviews.

Skills

NoC design

NoC topologies

RTL SystemVerilog

Cache coherency

Performance modeling

HBM/UCIe knowledge

Python scripting

Architecture leadership

Cycle-accurate simulation

Traffic analysis

Education

M.Tech/MS in EE/ECE/CS

Tools

NoC generators/IP

Job description

• LTST-L&T Semiconductor Technologies Limited

Posted On 09 Oct 2026

End Date 07 Apr 2027

Required Experience 10 - 15 years

Knowledge & Posting Location

NOC

BE

Job Description

NoC Design Lead (×2 openings)Location: Bangalore, India | Company: LTSCT — L&T Semiconductor Technologies LimitedReporting To: Chandra — Senior Architect, DC HW Systems | Experience: 10+ years (mandatory)Role SummaryWe are hiring two NoC Design Leads to own the stacked Network-on-Chip that forms the data backbone of xPU — 4 physical planes delivering 12 TB/s cross-section bandwidth. You will architect and implement coherency, routing, QoS, and bandwidth allocation across the BFOS arrays, banked SRAM, HBM controllers, UCIe links, and the host interface. This role is central to sustaining the extreme bandwidth and latency targets the compute architecture demands.

Key Responsibilities

• Architect and implement the 4-plane stacked NoC delivering 12 TB/s cross-section bandwidth across all on-chip and off-chip endpoints.
• Define topology, routing algorithms, virtual channels, and arbitration to guarantee deadlock-free, high-throughput data movement.
• Design QoS and bandwidth-allocation mechanisms balancing traffic between dual BFOS arrays, 512 SRAM banks, HBM controllers, UCIe, and host.
• Own the on-chip coherency protocol and its interaction with SRAM, HBM, and the host-interface coherency layer.
• Drive micro-architecture, RTL, and integration of routers, network interfaces, buffers, and clock-domain crossings.
• Model and analyze latency, bandwidth, and congestion via cycle-accurate simulation and traffic generators; close performance targets.
• Collaborate with PD on floorplan-aware NoC partitioning across the 4 physical planes and with DFT/verification on coverage.
• Define QoR/performance metrics, mentor engineers, and represent NoC in architecture and integration reviews.

Required Skills & Experience

• 10+ years designing on-chip interconnects/NoCs or coherent fabrics for high-performance SoCs.
• Deep understanding of NoC topologies (mesh, torus, crossbar, stacked/multi-plane), routing, flow control, and QoS.
• Strong grasp of cache-coherency protocols (MESI/MOESI-class, directory-based) and memory-consistency models.
• Expertise in RTL design (SystemVerilog) of routers, arbiters, buffers, and asynchronous/CDC interfaces.
• Hands-on performance modeling and analysis — cycle-accurate simulation, traffic modeling, bandwidth/latency closure.
• Experience with commercial or in-house NoC generators/IP and their integration methodology.
• Familiarity with high-bandwidth memory (HBM) and chiplet interconnect (UCIe) traffic characteristics.
• Proficiency in scripting (Python/Perl) for performance analysis and verification support.
• Strong micro-architecture, specification, and documentation skills.
• Demonstrated technical leadership and cross-team collaboration.

Preferred Qualifications

• Experience with multi-plane or 3D-stacked NoC architectures.
• Background in AI accelerator or GPU dataflow interconnects.
• Familiarity with formal verification of coherency/deadlock properties.
• M.Tech/MS in EE/ECE/CS or equivalent.