MTS-RTL Verification Engineer

Micron Technology, Inc; Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Benefits offered by this job

Medical, dental, and vision plans

Paid time-off

Paid family leave

Job summary

Micron Technology, Inc is looking for a Semiconductor Design Engineer MTS in Bengaluru, India. The role involves leading verification strategy, developing reusable verification environments, and ensuring high-speed operational readiness. Candidates must have expertise in SystemVerilog, UVM, and scripting languages.

The position offers comprehensive benefits including health care plans, income protection programs, paid family leave, and a robust time-off policy, fostering a supportive work environment.

Qualifications

• Expert in SystemVerilog and UVM, with a focus on detailed testing and constrained-random testing.
• Strong fundamentals in clocks, resets, FSMs, CDC, and debug.
• Proven experience in verifying high-speed digital designs in advanced process nodes.

Responsibilities

• Own verification strategy and planning; translate specifications into executable verification plans.
• Architect and develop scalable SystemVerilog/UVM verification environments.
• Mentor engineers and provide technical guidance.

Skills

SystemVerilog

UVM

Scripting proficiency (Python, Perl, or Tcl)

Debug tools

Job description

Key Responsibilities

• Own verification strategy and planning; translate specifications into executable verification plans and closure metrics
• Architect and develop scalable, reusable SystemVerilog/UVM verification environments
• Drive functional and code coverage closure, including assertions and targeted stimulus
• Lead debug and issue resolution across verification and design teams
• Provide verification status, risk assessment, and release readiness updates
• Ensure verification readiness for high‑speed operation, including initialization, reset, CDC, and mode‑transition scenarios
• Improve verification methodologies, automation, and regression efficiency
• Mentor engineers and provide technical guidance consistent with senior‑level expectations

Required Qualifications

• Expert in SystemVerilog and UVM, including verification passionate about detailed testing and constrained‑random testing, Formal Verification
• Strong fundamentals in clocks, resets, FSMs, CDC, and debug
• Proven experience verifying high‑speed digital designs in advanced process nodes
• Hands‑on experience with industry simulators, coverage, and debug tools
• Scripting proficiency (Python, Perl, or Tcl) for automation and productivity

Preferred

• Exposure to power‑aware verification
• Experience with high‑speed memory or adjacent subsystems
• Experience working with global, cross‑site teams

Success Indicators

• Stable, reusable verification environments with clear closure metrics
• Data‑driven coverage closure with minimal late escapes
• Early identification and resolution of high‑speed verification risks
• Effective and compliant use of Micron‑approved AI tools to augment verification activities, improve execution efficiency, and support continuous improvement

Job Profile(s): Semiconductor Design Eng MTS

Relocation level: TBD

Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations, enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave, as well as a robust paid time‑off program and paid holidays. For additional information regarding the benefit programs available, please see the Benefits Guide posted on Benefits | Micron Technology, Inc.

Micron is proud to be an equal‑opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.