MTS - ESD Design Engineer

Micron Technology, Inc; Bengaluru; On-site; INR 2,000,000 - 3,000,000; Full time

Job summary

Micron Technology, Inc is looking for an MTS - ESD Design Engineer in Bengaluru. The role involves leading ESD architecture and protection strategy for high-speed I/O portfolios including HBM and PCIe. Ideal candidates will have 15+ years of experience in ESD circuit design, strong command of SPICE simulators, and the ability to mentor junior engineers.

This position offers the opportunity to influence ESD-friendly process features and deliver production silicon that meets ESD and performance targets.

Qualifications

• 15+ years of hands-on experience in ESD circuit design and protection architecture.
• Expertise in high-speed I/O or mixed-signal chip environments.

Responsibilities

• Define and own ESD architecture and protection strategy.
• Lead silicon-level ESD failure analysis and root cause analysis.
• Serve as the ESD subject-matter guide across the organization.

Skills

ESD circuit design

High-speed I/O engineering

Interpersonal skills

SPICE simulators

Education

B.Tech / M.Tech / PhD in Electrical / Electronic Engineering

Tools

Spectre

HSPICE

Job description

Req. ID: JR95955 MTS - ESD Design Engineer

Responsibilities

Responsibilities will include, but are not limited to ESD Architecture Leadership & Strategy

• Define and own ESD architecture and protection strategy for high-speed I/O portfolios including:
  • HBM (High Bandwidth Memory) / DDR / LPDDR PHY I/Os
  • PCIe, USB, Ethernet, MIPI, and proprietary interfaces
• Lead ESD–I/O co‑design trade‑off decisions, balancing aggressive ESD targets (HBM / CDM / MM). Ultra‑low capacitance and leakage requirements
• Eye margin, jitter, bandwidth, return loss, and impedance matching
• Drive architectural choices for snapback clamps, rail clamps, diode steering networks, triggered and advanced ESD devices (technology‑dependent). Domain isolation and sequencing protection for sophisticated SoCs
• Advanced Circuit Design, Modeling & Signoff: Perform and guide ESD circuit design and analysis at block and full‑chip level
• Establish simulation methodologies for transient ESD stress (TLP‑equivalent behavior), dynamic clamp triggering and current handling, I/O performance impact (cap loading, ringing, overshoot/undershoot)
• Own ESD modeling correlation: Work with device/modeling teams on compact models (dynamic R, triggering, CV behavior). Drive correlation between SPICE simulations, TLP/VF‑TLP, and silicon results. Act as the final technical authority for ESD Design reviews and signoff
• Silicon Debug, Reliability & Qualification Ownership: Lead silicon‑level ESD failure analysis across products and generations. Drive root cause analysis for HBM/CDM failures, leakage and performance degradation, latch‑up and substrate‑coupling issues
• Collaborate deeply with reliability: Define corrective actions and preventive methodologies. Own ESD qualification strategies and ensure first‑pass silicon success
• Physical Design, Layout & Technology Engagement: Define company‑wide layout guidelines for ESD devices, current uniformity, ballasting, guard rings, substrate/well engineering and isolation standard processes, power clamp placement and return path integrity
• Partner with technology, process, and PDK teams to influence ESD‑friendly process features, enable scalable ESD solutions in sophisticated node, and ensure ESD robustness across multiple packages and IO ring configurations
• Multi‑functional & Interpersonal Leadership: Serve as the ESD subject‑matter guide (SME) across the organization. Provide strategic guidance to I/O and PHY design teams, PDN, package, and board‑level engineers, product engineering and manufacturing. Mentor and technically develop junior and senior ESD/design engineers, drive methodology reuse, IP standardization, and design standard processes across programs
• Consistent track record of delivering production silicon meeting aggressive ESD and performance targets. Leading ESD technical decisions for sophisticated, high‑volume products
• Deep expertise in HBM, CDM, MM, latch‑up mechanisms & high‑speed signal integrity fundamentals and constraints
• Strong command of SPICE‑based simulators (Spectre, HSPICE) & physical layout review and ESD signoff flows
• Leadership & Soft Skills: Recognized technical authority with strong executive‑level interpersonal skills, ability to make and defend data‑driven architectural trade‑offs, mentor‑first attitude, passion for growing technical talent, comfort operating in ambiguous, fast‑paced, first‑principles problem spaces

What Success Looks Like

• ESD requirements consistently met without compromising high‑speed I/O performance
• Predictable, silicon‑correlated ESD signoff across projects
• Reusable ESD IP and methodologies deployed across multiple products and nodes

Requirements / Qualification

• B.Tech / M.Tech / PhD in Electrical / Electronic Engineering or related field
• 15+ years of hands‑on experience in ESD circuit design and protection architecture & high‑speed I/O or mixed‑signal chip environments

Other Information

Job Profile(s): Semiconductor Design Eng MTS

Relocation level: (TBD)

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.