MTS - ESD Design Engineer

Micron Technology; Bengaluru; On-site; INR 2,000,000 - 3,000,000; Full time

Job summary

Micron Technology seeks an experienced professional in Bengaluru to lead ESD architecture and strategy for high-speed I/O portfolios. The ideal candidate will possess a B.Tech/M.Tech/PhD in Electrical/Electronic Engineering and over 15 years of hands-on experience in ESD circuit design and protection architecture in high-speed I/O or mixed-signal chip environments. Responsibilities include co-design decisions, ESD circuit analysis, and collaboration with reliability teams to ensure high-performance outcomes.

Qualifications

• 15+ years of hands-on experience in ESD circuit design and protection architecture and high-speed I/O or mixed-signal chip environments.

Responsibilities

• Lead ESD Architecture Leadership & Strategy.
• Define and own ESD architecture and protection strategy.
• Drive architectural choices for ESD devices.
• Perform and guide ESD circuit design and analysis.
• Collaborate deeply with reliability teams.

Skills

ESD circuit design

High-speed I/O design

Mixed-signal chip environments

SPICE-based simulators

Leadership and mentorship

Education

B.Tech / M.Tech / PhD in Electrical / Electronic Engineering

Job description

Responsibilities

Responsibilities will include, but are not limited to ESD Architecture Leadership & Strategy. Define and own ESD architecture and protection strategy for high-speed I/O portfolios including:

• HBM (High Bandwidth Memory) / DDR / LPDDR PHY I/Os
• PCIe, USB, Ethernet, MIPI, and proprietary interfaces
• Lead ESD–I/O co-design trade-off decisions, balancing: Aggressive ESD targets (HBM / CDM / MM). Ultra-low capacitance and leakage requirements
• Eye margin, jitter, bandwidth, return loss, and impedance matching
• Drive architectural choices for: Snapback clamps, rail clamps, diode steering networks. Triggered and advanced ESD devices (technology-dependent). Domain isolation and sequencing protection for sophisticated SoCs
• Advanced Circuit Design, Modeling & Signoff: Perform and guide ESD circuit design and analysis at block and full-chip level.
• Establish simulation methodologies for: Transient ESD stress (TLP-equivalent behavior). Dynamic clamp triggering and current handling. I/O performance impact (cap loading, ringing, overshoot/undershoot).
• Own ESD modeling correlation: Work with device/modeling teams on compact models (dynamic R, triggering, CV behavior). Drive correlation between SPICE simulations, TLP/VF-TLP, and silicon results. Act as the final technical authority for ESD Design reviews and signoff.
• Silicon Debug, Reliability & Qualification Ownership: Lead silicon-level ESD failure analysis across products and generations.
• Drive root cause analysis for: HBM/CDM failures. Leakage and performance degradation. Latch-up and substrate-coupling issues
• Collaborate deeply with reliability: Define corrective actions and preventive methodologies. Own ESD qualification strategies and ensure first-pass silicon success.
• Physical Design, Layout & Technology Engagement: Define company-wide layout guidelines for ESD devices. Current uniformity, ballasting, guard rings. Substrate/well engineering and isolation standard processes. Power clamp placement and return path integrity
• Partner with technology, process, and PDK teams to: Influence ESD-friendly process features. Enable scalable ESD solutions in sophisticated node & Ensure ESD robustness across multiple packages and IO ring configurations.
• Multi-functional & Interpersonal Leadership: Serve as the ESD subject-matter guide (SME) across the organization.
• Provide strategic guidance to: I/O and PHY design teams. PDN, package, and board-level engineers. Product engineering and manufacturing. Mentor and technically develop junior and senior ESD/design engineers & Drive methodology reuse, IP standardization, and design standard processes across programs.
• Consistent track record of: Delivering production silicon meeting aggressive ESD and performance targets. Leading ESD technical decisions for sophisticated, high-volume products.
• Deep expertise in: HBM, CDM, MM, latch-up mechanisms & High-speed signal integrity fundamentals and constraints
• Strong command of: SPICE-based simulators (Spectre, HSPICE) & Physical layout review and ESD signoff flows
• Leadership & Soft Skills: Recognized technical authority with strong executive-level interpersonal skills. Ability to make and defend data-driven architectural trade-offs. Mentor-first attitude with passion for growing technical talent. Comfort operating in ambiguous, fast-paced, first-principles problem spaces.

What Success Looks Like

• ESD requirements consistently met without compromising high-speed I/O performance.
• Predictable, silicon-correlated ESD signoff across projects.
• Reusable ESD IP and methodologies deployed across multiple products and nodes.

Requirements / Qualification

• B.Tech / M.Tech / PhD in Electrical / Electronic Engineering or related field.
• 15+ years of hands-on experience in ESD circuit design and protection architecture and high-speed I/O or mixed-signal chip environments.