Emulation Architect (ZeBu / HAPS)

Wipro; Ernakulam, Hyderabad; Hybride; INR 4 200 000 - 6 800 000; Plein temps

Avantages offerts par ce poste

Palladium exposure

Veloce exposure

Hybrid emulation platforms

Résumé du poste

Wipro is seeking an Emulation Architect (ZeBu/HAPS) to lead pre-silicon validation and emulation programs across multi-FPGA platforms. You will own design partitioning, platform selection, and bring-up strategies for enterprise SoC projects.

You will drive engineering collaboration with RTL, DV, DFT and SW teams, mentor engineers, and support customer reviews. This role requires 12+ years of relevant experience and a strong ARM/RISC‑V emulation background.

Qualifications

• 15+ years in ASIC/SoC pre-silicon validation, with 8+ years in ZeBu and HAPS emulation.
• Proven delivery of multiple SoC emulation or prototyping programs from compile to bring‑up.
• Expert in design partitioning, FPGA‑friendly RTL, clock and memory mapping, and timing closure.
• Strong with AMBA (AXI/AHB/APB), PCIe, Ethernet, USB and DDR/LPDDR subsystems and their emulation models.
• Experience with ARM- or RISC‑V‑based SoC bring-up, firmware integration and OS boot on emulators.
• Scripting and automation in Python, Tcl or Perl; ability to debug at waveform, trace and system level.

Responsabilités

• Define emulation and prototyping strategy: platform selection (ZeBu/HAPS), capacity planning.
• Own design partitioning, multi-FPGA / multi-board mapping, clocking, timing and interconnect for emulation targets.
• Drive ZeBu and HAPS compile flows, bring-up, runtime performance and debug visibility.
• Build transactor, co-emulation and virtual-platform environments for firmware, OS and system-level validation.
• Run hardware/software co-validation, power and performance analysis, and regression automation on emulators.
• Partner with RTL, DV, DFT and SW teams; mentor emulation engineers and lead customer technical reviews.

Connaissances

ASIC/SoC validation

ZeBu/HAPS emulation

SoC prototyping

Design partitioning

AMBA protocols (AXI/AHB/APB)

PCIe / Ethernet / USB

DDR/LPDDR subsystems

ARM/RISC-V bring-up

Firmware integration & OS boot

Scripting (Python/Tcl/Perl)

Waveform/trace debugging

Outils

Palladium exposure

Veloce exposure

Description du poste

Greetings from Wipro

We are pleased to share an exciting opportunity for the Emulation Architect (ZeBu / HAPS) role at Wipro. Please find the role details below

Role Details

Requirement Name : Emulation Architect (ZeBu / HAPS)

Experience:12Years +

Work location : Bengaluru / Hyderabad / Kochi / Chennai / Any LocationWork Mode : Hybrid

Job Type: Full-Time with Wipro

JD

What You Bring(Mandatory:

• 15+ years in ASIC/SoC pre-silicon validation, with 8+ years of hands-on ZeBu and HAPS emulation / prototyping.
• Proven delivery of multiple SoC emulation or prototyping programs, from compile through system bring-up.
• Expert in design partitioning, FPGA-friendly RTL, clock and memory mapping, and emulation timing closure.
• Strong with AMBA (AXI/AHB/APB), PCIe, Ethernet, USB and DDR/LPDDR subsystems and their emulation models.
• Experience with ARM- or RISC-V-based SoC bring-up, firmware integration and OS boot on emulators.
• Scripting and automation in Python, Tcl or Perl; ability to debug at waveform, trace and system level.
  

What You Will Do:

• Define emulation and prototyping strategy: platform selection (ZeBu / HAPS), capacity planning and milestones.
• Own design partitioning, multi-FPGA / multi-board mapping, clocking, timing and interconnect for emulation targets.
• Drive ZeBu and HAPS compile flows, bring-up, runtime performance and debug visibility.
• Build transactor, co-emulation and virtual-platform environments for firmware, OS and system-level validation.
• Run hardware/software co-validation, power and performance analysis, and regression automation on emulators.
• Partner with RTL, DV, DFT and SW teams; mentor emulation engineers and lead customer technical reviews.

Good to Have :

• Palladium or Veloce exposure
• Hybrid emulation, virtual platforms and transaction-level co-simulation
• Post-silicon bring-up and chiplet / multi-die validation