Zebu Emulation Engineer

Happiest Minds Technologies; Bengaluru; On-site; INR 3,000,000 - 4,200,000; Full time

Job summary

Happiest Minds Technologies in Bengaluru, India, is seeking a Senior Emulation Engineer to support pre-silicon validation of next-generation processor and SoC products using Synopsys ZeBu emulation platforms. The role covers emulation bring-up, debug, and performance optimization of complex designs.

Responsibilities include deploying RTL on ZeBu, developing testbenches and emulation flows, SoC/IP bring-up, and coordinating with firmware for early boot validation.

Qualifications

• 5-8 years of experience in ASIC/SoC verification, validation, or emulation.
• Hands-on experience with Synopsys ZeBu platforms.
• Strong knowledge of Verilog/SystemVerilog and UVM.
• Experience with SoC architectures and bus protocols such as AXI/AHB/APB.
• Proficiency in Python, TCL, or Shell scripting.
• Strong debugging and problem-solving skills.

Responsibilities

• Deploy and validate RTL designs on Synopsys ZeBu emulation platforms.
• Develop and maintain synthesizable testbenches and emulation flows.
• Perform SoC/IP bring-up, functional validation, and debug.
• Support firmware and software teams for early boot and system validation.
• Analyze failures, debug RTL issues, and drive root-cause resolution.
• Automate emulation and regression flows using scripting languages.

Skills

ASIC/SoC verification

ZeBu emulation

Verilog/SystemVerilog

UVM

AXI/AHB/APB

Scripting (Python/TCL/Shell)

Debugging

Tools

Synopsys ZeBu

Job description

We are seeking a motivated Senior Emulation Engineer to support pre-silicon validation of next-generation processor and SoC products using Synopsys ZeBu emulation platforms. The role involves emulation bring-up, hardware-software co-validation, debug, and performance optimization of complex SoC designs.

Key Responsibilities

• Deploy and validate RTL designs on Synopsys ZeBu emulation platforms.
• Develop and maintain synthesizable testbenches and emulation flows.
• Perform SoC/IP bring-up, functional validation, and debug.
• Support firmware and software teams for early boot and system validation.
• Analyze failures, debug RTL issues, and drive root-cause resolution.
• Automate emulation and regression flows using scripting languages.

Required Skills

• 5-8 years of experience in ASIC/SoC verification, validation, or emulation.
• Hands-on experience with Synopsys ZeBu platforms.
• Strong knowledge of Verilog/SystemVerilog and UVM.
• Experience with SoC architectures and bus protocols such as AXI/AHB/APB.
• Proficiency in Python, TCL, or Shell scripting.
• Strong debugging and problem-solving skills.