Firm ware Engineer II

Cadence Design Systems, Inc.; Bengaluru; On-site; INR 1,500,000 - 2,500,000; Full time

Job summary

Cadence Design Systems in Bengaluru is seeking a Design Engineer II to join a dynamic team developing physical layer IPs for high-speed SERDES. You will work with PHY digital and mixed-signal architects, contribute to firmware architecture, and implement features from architecture to validation.

The role involves building system-level prototype software for adaptation and equalization, verifying with the test teams, supporting post-silicon characterization, and creating comprehensive firmware

Qualifications

• B.Tech/B.E. with 4 years of study or M.Tech with 2 years in Electrical/Electronics Engineering.
• Strong programming skills in C/C++ and Python.
• Good problem-solving and communication abilities.
• Familiarity with FuSa compliance is a plus.
• Understanding of wireline communication and DSP is a plus.

Responsibilities

• Collaborate with PHY digital and mixed-signal architects to design firmware functions.
• Contribute to firmware architecture and implementation of features.
• Develop system-level prototype software for adaptation, equalization, and control algorithms for high-speed SERDES.
• Implement features and coordinate with verification and validation teams.
• Support FuSa compliant firmware development and testing.
• Create and maintain firmware documentation.

Skills

C/C++

Python

Problem solving

Communication skills

Education

B.Tech/B.E. in Electrical/Electronics Engineering

M.Tech in Electrical/Electronics Engineering

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Description Design Engineer II This is an opportunity to join a dynamic and growing team of experienced engineers developing physical layer IP’s for industry-standard high-speed serial-link protocols. The successful candidate will ideally be a highly motivated self-starter who can work independently to complete assigned tasks and collaborate with other members to achieve project milestones. It is expected that the candidate will contribute during all phases of firmware development for high speed SERDES - from architecture development to implementation, verification, testing and customer deployment.

Responsibilities

• Work closely with PHY digital and mixed signal architects to figure out the details of FW functions and sequences.
• Contribute during firmware architecture development and implementation of the defined firmware features.
• Help to build system level prototype control software to develop/validate adaptation, equalization, and control algorithms for high speed SERDES.
• Implement assigned FW features and work closely with verification[simulation] and validation team to ensure the functionality and robustness of the implemented features.
• Support FuSa compliant firmware development.
• Work closely with verification and validation team to develop and execute test plans for FuSa compliant firmware.
• Support of Validation team during electrical and system characterization during post-silicon testing.
• Identify any FW and HW related functionality and performance issues and implement any necessary FW improvements to address these issues.
• Support Product Engineering, System Validation and Design team to debug IP issues during customer deployment of the IP and provide hot fixes.
• Create and maintain comprehensive documentation related to firmware design, development, bug fixes and compliance testing.

Desired Skills

• B.Tech with 4yrs or M.Tech with 2 yrs in Electrical/Electronics Engineering
• Solid programming knowledge in C/C++ and Python
• Strong problem-solving and communication skills
• Understanding of wireline communication principles and digital signal processing techniques is a plus
• Knowledge in mixed signal circuit design is a plus
• Experience with silicon validation process and debug is a plus
• Experience with digital verification environment and tools is a plus
• Understanding of FuSa compliance is a plus

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