Low Power Design Engineer (RTL)

Advanced Micro Devices; Hyderabad; On-site; INR 1,500,000 - 2,800,000; Full time

Benefits offered by this job

AMD benefits at a glance

Job summary

AMD Hyderabad invites applications for a role to plan, build and integrate low‑power features in AMD’s graphics processor IP, delivering bug‑free final designs.

You will work with RTL engineers across sites, apply UPF/CPF, DVFS, power gating and clock gating, and drive power sign‑off using industry tools to meet design budgets.

Require strong digital IC/SoC design knowledge, Verilog/SystemVerilog, and a Bachelors or Masters in Computer or Electrical Engineering.

Qualifications

• Strong knowledge of digital IC/SoC design flow.
• Proficiency with UPF (Unified Power Format) and CPF (Common Power Format).
• Experience with power-aware simulation and verification methodologies.
• Familiarity with industry EDA tools (Synopsys, Cadence, Siemens/Mentor).
• Understanding of RTL design (Verilog/SystemVerilog).
• Knowledge of static timing, synthesis and implementation flows.

Responsibilities

• Define SoC and subsystem power architecture.
• Develop and maintain power intent using UPF/CPF methodologies.
• Implement low-power techniques such as power gating, clock gating, multi‑voltage domains, DVFS, retention and isolation strategies.
• Collaborate with RTL designers to integrate low‑power features.
• Run and debug low‑power checks using EDA tools.
• Perform power estimation, analysis, and optimization throughout the design cycle.
• Drive power signoff activities and ensure compliance with project power budgets.
• Support functional verification teams in low‑power verification planning and execution.

Skills

Digital IC/SoC design

UPF

CPF

Low‑power design methodologies

Power‑aware verification

EDA tools

Verilog/SystemVerilog

Static timing

Synthesis/implementation

Power analysis tools

Education

Bachelor's or Master's in Computer/Electrical Engineering

Job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them.

AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward.

THE ROLE:

The focus of this role is to plan, build, Design/Integration of new and existing features for AMD’s graphics processor IP, resulting in no bugs in the final design.

THE PERSON:

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

Key Responsibilities

• Define SoC and subsystem power architecture.
• Develop and maintain power intent using UPF/CPF methodologies.
• Implement low-power techniques such as:
• Power gating
• Clock gating
• Multi-voltage domains
• Dynamic Voltage and Frequency Scaling (DVFS)
• Retention and isolation strategies
• Collaborate with RTL designers to integrate low‑power features.
• Run and debug low‑power checks using EDA tools.
• Perform power estimation, analysis, and optimization throughout the design cycle.
• Drive power signoff activities and ensure compliance with project power budgets.
• Support functional verification teams in low‑power verification planning and execution.

Required Skills

Technical Skills

• Strong knowledge of digital IC/SoC design flow.
• Expertise in:
• UPF (Unified Power Format)
• CPF (Common Power Format)
• Power‑aware simulation and verification
• Low‑power design methodologies
• Experience with industry‑standard EDA tools (Synopsys, Cadence, Siemens/Mentor).
• Understanding of RTL design (Verilog/SystemVerilog).
• Knowledge of static timing, synthesis, and implementation flows.
• Familiarity with power analysis tools and methodologies.

Programming/Scripting

• Tcl
• Perl/Python
• Shell scripting

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.