Senior/Lead STA Engineer

Sop Technology Services; Bengaluru; On-site; INR 3,000,000 - 6,000,000; Full time

Job summary

Sop Technology Services in Bengaluru/Hyderabad invites applications for a Senior/Lead STA Engineer to lead timing signoff and full-chip timing closure for next-generation silicon.

Candidates bring 8+ years of STA experience, in-depth PrimeTime, MMMC, and LVF OCVs on 7nm/5nm process nodes, and proven technical leadership.

Qualifications

• Strong expertise in Static Timing Analysis (STA) and Timing Signoff.
• Hands-on experience with PrimeTime, MMMC, OCV/AOCV/POCV/LVF.
• Full-chip timing closure and signoff ownership.
• Experience with advanced nodes (7nm/5nm/3nm and below).
• Exposure to timing architecture and methodology development.
• Multi-die, Chiplet, or 3D-IC timing experience is a plus.
• Technical leadership and mentoring capabilities.

Responsibilities

• Drive timing architecture, timing signoff methodology, and full-chip timing closure for high-performance silicon.
• Provide technical leadership and mentoring for STA efforts across projects.
• Collaborate with design and verification teams to ensure timing objectives are met.

Skills

Static Timing Analysis

Timing Signoff

PrimeTime

OCV/AOCV/POCV/LVF

Full-Chip Timing

Advanced nodes 7nm/5nm/3nm

Timing Architecture

Leadership

Tools

PrimeTime

MMMC

OCV/AOCV/POCV/LVF

Job description

Hiring: Senior/Lead STA Engineer

Location: Bengaluru / Hyderabad (WFO)
Experience: 8-20 Years
Notice Period: Immediate Joiners Preferred

Join a team working on next-generation semiconductor products and complex SoC designs at advanced technology nodes. This is an opportunity to drive timing architecture, timing signoff methodology, and full-chip timing closure for high-performance silicon.

What You'll Bring:

• Strong expertise in Static Timing Analysis (STA) and Timing Signoff
• Hands-on experience with PrimeTime, MMMC, OCV/AOCV/POCV/LVF
• Full-chip timing closure and signoff ownership
• Experience with advanced nodes (7nm/5nm/3nm and below)
• Exposure to timing architecture and methodology development
• Multi-die, Chiplet, or 3D-IC timing experience is a plus
• Technical leadership and mentoring capabilities

Target Titles: Lead STA Engineer | Principal STA Engineer | Staff STA Engineer | Timing Architect | Timing Signoff Lead | Full-Chip Timing Lead

If you're looking for a high-impact role where you can solve challenging timing problems and influence next-generation silicon designs, we'd love to connect with you.