Lead MTS Physical Design

Rambus.com; Bengaluru; On-site; INR 1,800,000 - 2,500,000; Full time

Benefits offered by this job

Competitive compensation package

Equity and employee benefits

Job summary

Rambus.com in Bangalore is seeking an exceptional Lead Physical Design Engineer to own end-to-end physical implementation for major IP blocks. The ideal candidate will have at least 10 years of experience in physical design with a strong understanding of Cadence tools.

You will collaborate with various teams to ensure robust designs, mentor junior engineers, and contribute to the culture of continuous improvement within the Silicon IP team. Rambus offers a competitive compensation package, including salary, bonus, equity, and benefits.

Qualifications

• Minimum of 10 years of experience, with 8 years in physical design.
• Detailed knowledge of EDA tools and flows is required.
• Experience in Tcl/Tk and PERL is a plus.

Responsibilities

• Own end-to-end physical implementation for major IP blocks.
• Develop and optimize floorplans and perform detailed static timing analysis.
• Collaborate with various teams to achieve project milestones.

Skills

End-to-end physical implementation

Cadence Innovus

Physical design

Tcl/Tk

PERL

Education

Bachelors degree in EE/ECE

Tools

EDA tools

Cadence foundation flows

Job description

Overview

Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional Lead Physical Design Engineer to join our Silicon IP team in Bangalore. In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer.

Responsibilities

• Own end-to-end physical implementation for major IP blocks and/or full-chip designs.
• Develop and optimize floorplans (macro placement, IO ring planning, power grid design, congestion/area/timing analysis)
• Execute place-and-route, clock tree synthesis, and timing closure using industry-standard tools (Cadence Innovus).
• Perform detailed static timing analysis (STA) and drive sign-off across PVT corners and operating modes.
• Identify and resolve physical verification issues (DRC/LVS/ERC) in close partnership with process/CAD/foundry teams, ensuring robust manufacturability.
• Automate design flows (e.g., hierarchical PNR, IO ring automation, PG) to improve efficiency and quality; contribute to continuous flow enhancements.
• Collaborate with RTL, DFT, verification, package, and library teams to meet performance, power, and area (PPA) targets and project milestones.
• Mentor and coach junior engineers, sharing best practices in physical design and advancing team capability.
• Document methodologies and contribute to best practices, supporting a culture of learning and continuous improvement.
• Demonstrate Rambus values by being agile in adapting to changing business needs, leading by example, and striving for best-in-class results.

Qualifications

• Must have minimum Bachelors degree in EE/ECE (degree’s related to electronics) from a reputed institute.
• Must have at least 10 years of experience, out of which at least 8 years should be related to physical design at chip level / block level.
• Must have detailed knowledge of EDA tools and flows, Cadence related foundation flows and RTL2GDS flow is desired.
• Experience in Tcl/Tk, PERL is a Plus.

Compensation

Rambus offers a competitive compensation package, including base salary, bonus, equity and employee benefits.

Equal Employment Opportunity

Rambus is proud to be an Equal Employment Opportunity and Affirmitive Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, or other applicable legally protected characteristics.

Disability Accommodations

Rambus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans during our job application procedures. If you require assistance or an accommodation due to a disability, please feel free to inform us in your application.