Silicon Micro Architecture And IP Design Lead Google Cloud

Google LLC; Bengaluru; On-site; INR 4,500,000 - 7,500,000; Full time

Job summary

Google LLC in Bengaluru, India is seeking a Senior ASIC engineer to lead the development of IPs and subsystems, focusing on TPU architecture and AI/ML hardware acceleration. You will verify complex digital designs and collaborate with architecture, firmware and software teams to drive feature closure.

The role emphasizes cutting-edge performance, efficiency and integration in a hyperscale environment, with opportunities to shape TPU integration within AI-driven systems.

Qualifications

• Bachelor's degree or equivalent practical experience in EE/CS or related field.
• 10+ years of experience in ASIC development with Verilog/SystemVerilog and VHDL.
• Experience in micro-architecture and design of IPs and subsystems.
• Experience in ASIC design verification, synthesis, timing/power analysis, and DFT.

Responsibilities

• Drive development of complex IPs and subsystems along with a team of engineers.
• Own micro-architecture and implementation of IPs and subsystems.
• Work with architecture, firmware and software teams to drive feature closure and develop micro-architecture specifications.
• Drive design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams.
• Identify and drive power, performance and area improvements for the domains owned.

Skills

Verilog

SystemVerilog

VHDL

IP design

ASIC verification

DFT

Synthesis

Education

Masters or PhD in EE/CS

Tools

Python

Perl

Job description

Job Description:

Minimum qualifications:

• Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  
• 10 years of experience in ASIC development with Verilog/SystemVerilog, and Vhsic Hardware Description Language (VHDL).
• Experience in micro-architecture and design of IPs and Subsystems.
• Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT).

Preferred qualifications:

• Masters degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  
• Experience with scripting languages (e.g., Python or Perl).
• Experience in SoC designs and integration flows.
• Knowledge of business architectures, fabrics/NoC, processor design, accelerators, or memory hierarchies.
• Knowledge of high-performance and low-power design techniques.

About the job:

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Googles direct-to-consumer products. Youll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Googles most demanding AI/ML applications. You will be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Googles TPU. You will contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML driven systems.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

Were the driving force behind Googles groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Responsibilities:

• Drive development of complex IPs and subsystems along with a team of engineers.
• Own micro-architecture and implementation of IPs and subsystems.
• Work with architecture, firmware and software teams to drive feature closure and develop micro-architecture specifications.
• Drive design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams.
• Identify and drive power, performance and area improvements for the domains owned.