Lead Engineer (IP Design & Microarchitecture)

Siemens; Dadri; On-site; INR 2,200,000 - 3,500,000; Full time

Job summary

Siemens EDA in India is seeking a senior RTL design engineer to develop, test, and optimize design IPs for Power, Performance, and Area (PPA). You will implement in SystemC/C++ and drive latency, throughput, and power goals within a tight design/verification cycle.

The role requires strong RTL experience (Verilog/SystemVerilog) and hands-on work with HLS for ASICs or FPGAs, plus ability to translate complex DSP algorithms into efficient micro/RTL architectures.

Qualifications

• 5-10 years of experience in RTL design (Verilog, SystemVerilog, digital microarchitecture).
• A Bachelor's/Master’s degree pr PhD Scholars with 6 years of relevant experience are preferred.
• Proven experience in breaking down complex digital signal processing algorithms into Micro/RTL architecture, while effectively managing cost and quality trade-offs.
• Proficiency in coding with C/C++/Python/Bash.
• Experience with High-Level Synthesis (HLS) for ASICs or FPGAs is a significant advantage.
• Knowledge of basic processor architecture.
• Experience with the full ASIC design cycle (from specification through bring-up) is preferred.

Responsibilities

• Develop, test, maintain, and improve design IPs for optimal Power, Performance, and Area (PPA).
• Implement functionality in SystemC/C++ and ensure designs meet stringent Latency, Throughput, Area, and Power goals.
• Perform comprehensive power, area, and performance trade-off analyses to identify the most efficient solutions.
• Leverage High-Level Synthesis (HLS) to rapidly iterate and evaluate a wide range of possible implementations, narrowing down to the best-suited version.
• Drive coverage closure and meet all other sign-off criteria for IPs within a high-level design and verification environment.
• Author detailed design documents that clearly articulate your architectural and implementation choices.

Skills

RTL design

SystemVerilog

Verilog

C/C++/Python

HLS

processor architecture

ASIC/FPGA design

Education

Bachelor's or Master's degree

PhD (preferred)

Tools

High-Level Synthesis (HLS)

Job description

Siemens EDA is a global technology leader in Electronic Design Automation (EDA) software. Our innovative tools empower companies worldwide to develop highly advanced electronic products faster and more cost-effectively. We're pushing the boundaries of technology and physics, enabling our customers to deliver superior products in the increasingly complex world of chip, board, and system design.

What you'll do:

• Develop, test, maintain, and improve design IPs for optimal Power, Performance, and Area (PPA).
• Implement functionality in SystemC/C++ and ensure designs meet stringent Latency, Throughput, Area, and Power goals.
• Perform comprehensive power, area, and performance trade-off analyses to identify the most efficient solutions.
• Leverage High-Level Synthesis (HLS) to rapidly iterate and evaluate a wide range of possible implementations, narrowing down to the best-suited version.
• Drive coverage closure and meet all other sign-off criteria for IPs within a high-level design and verification environment.
• Author detailed design documents that clearly articulate your architectural and implementation choices.

What you'll bring:

• 5-10 years of experience in RTL design (Verilog, SystemVerilog, digital microarchitecture).
• A Bachelor's/Master’s degree pr PhD Scholars with 6 years of relevant experience are preferred.
• Proven experience in breaking down complex digital signal processing algorithms into Micro/RTL architecture, while effectively managing cost and quality trade-offs.
• Proficiency in coding with C/C++/Python/Bash.
• Experience with High-Level Synthesis (HLS) for ASICs or FPGAs is a significant advantage.
• Knowledge of basic processor architecture.
• Experience with the full ASIC design cycle (from specification through bring-up) is preferred.

We are Siemens

A collection of over 377,000 minds building the future, one day at a time, in over 200 countries. We're dedicated to equality and welcome applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit, and business need. Bring your curiosity and creativity and help us shape tomorrow!

We offer a comprehensive reward package which includes a competitive basic salary, bonus scheme, generous holiday allowance, pension, and private healthcare.

Transform the everyday!